Device for synchronizing a binary data train in relation to a reference train
AssigneeCompagnie Industrielle des Telecommunications Cit-Alcatel
InventorsJean-Louis Lagarde, Gilles Gauriat
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Abstract
The invention comes within the field of digital transmission and concerns e synchronization of two bit trains in relation to the beginning of a frame. According to the invention, one of the trains crosses a memory of the FIFO type, whose writing speed corresponds to the frequency of that train and whose reading is controlled by a detector of the locking word in that frame and by a signal indicating the synchronization of the two trains. Application: digital PCM terminals comprising thirty telephone channels.
Claims2
A device for synchronizing a binary data series train in relation to a reference train, the two trains having identical frequencies and being subdivided by predetermined locking bits into frames of identical lengths, the device comprising:
- a series/parallel-type first converter receiving the binary train in series and delivering this train, cut up randomly in words of q bits (q = 2, 3, . . . );
- a FIFO-type memory having q bits per memory cell therein and receiving words at a regular writing speed of l/q of the frequency;
- a parallel/series-type second converter receiving the output of said memory;
- a decoder for detecting the predetermined locking bits from an output train of said second converter;
- logic control means for receiving a pulse clock signal and frame synchronization signal of the reference train as well as the output of said decoder, for controlling the reading operation of said memory;
- and gate means for delivering the binary train to a synchronized output of the device.
Dependencies are inferred from the claim text.