Method and apparatus for plating the posts of a semiconductor chip header
AssigneeNational Semiconductor Corporation
InventorCarl E. Bernardi
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AssigneeNational Semiconductor Corporation
InventorCarl E. Bernardi
Estimating the term…
A method and apparatus for plating the posts of a semiconductor chip header is described. A means is provided for orientating the headers and feeding them in single file to a predetermined position in the apparatus. A transporting means is provided for transporting the headers from the feeding means over a plating bath such that the posts of the header are immersed in the bath. Attached to the transporting means is a plurality of clamping assemblies. Each of the clamping assemblies includes a knife-like member for electrically insulating the thru-leads of the header from its envelope lead and means for clamping the thru-leads of the header to the knife-like member. The clamping means of the clamping assemblies also include means for coupling a source of potential between the plating bath and the thru-leads clamped therein.
An apparatus for plating the posts of a semiconductor chip header having at least one envelope lead electrically connected to a metallic envelope enclosing said header and a predetermined number of thru-leads which are insulated from and pass through said envelope for forming posts on the top thereof comprising:
An apparatus for plating the posts of a semiconductor chip header having at least one envelope lead electrically connected to a metallic envelope enclosing said header and a predetermined number of thru-leads which are insulated from and pass through said envelope for forming posts on the top thereof comprising:
Dependencies are inferred from the claim text.
Electroplating characterised by the process; Pretreatment or after-treatment of workpieces: electroplating of selected surface areas
Apparatus for electrolytic coating of small objects in bulk: with means for moving the objects individually through the apparatus during treatment
Processes for the electrolytic or electrophoretic production of coatings
Term ended 30 Aug 1994 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention is related to a method and apparatus for plating semiconductor chip headers in general and, in particular, to a method and apparatus for plating header posts.
A typical semiconductor chip header includes a body member. The body member comprises an insulating material encased in a metallic envelope for forming a chip receiving surface on the top thereof. Extending from the bottom of the body member is a plurality of leads. Normally one of the leads, called for convenience an envelope lead, is electrically connected to the envelope for providing an electrical connection to a chip bonded to the top of the envelope. The others of said plurality of leads are disposed to pass through said header body and are electrically insulated from said envelope for forming posts on the top thereof. The posts are typically located outwardly of the chip receiving area and are provided to be connected, in the course of fabricating a solid state device, to selected parts of the chip as by thin wires or the like.
In the process of fabricating semiconductor devices, it is frequently necessary to plate the posts. Heretofore, this has been done by inserting the headers in an inverted position in individual holes in the bottom of a supporting container or belt such that the posts of the headers and a portion of the body project downwardly therethrough. The posts and the portion of the header body projecting through the holes are then immersed in a plating solution.
The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the accompanying drawings in which
FIG. 1 is a top perspective view showing the posts of a typical header which can be plated with the method and apparatus of the present invention.
FIG. 2 is a bottom perspective view of the envelope and thru-leads of the header of FIG. 1.
Referring to FIGS. 1 and 2, there is shown a header 1. Header 1 comprises a body member of insulating material 2 encapsulated in a metallic envelope 3. On the top of header 1 there is a generally flat surface forming semiconductor chip receiving surface 4 on which is bonded a semiconductor chip (not shown) during the fabrication of a semiconductor device using the header 1. Extending from the bottom of header 1 are three leads: 5, 6 and 7. Lead 6 is attached directly to the metallic envelope 2. Leads 5 and 7 are insulated from envelope 2 and pass through the material 2 of header 1 for forming on the top thereof, respectively, a pair of posts 8 and 9. In the fabrication of a semiconductor device using the header 1, the posts 8 and 9 are employed for making an electrical connection by means of thin wires or the like (not shown) attached thereto and to selected parts of a chip bonded on the surface 4.
As pointed out hereinabove, it is frequently necessary to plate the posts of a header for providing good long-term conductivity between the posts and a wire connected thereto. Header 1 is representative of the types of headers having posts which can be plated by means of the present invention. Thus, while the posts of other types of headers may also be plated, it is believed sufficient for purposes of describing the present invention to limit the description to the plating of headers represented by header 1.
Referring to the drawings and presently, in particular, to FIG. 3, there is provided in accordance with the present invention, a conventional header bin or hopper assembly 10. Hopper 10 is provided for orientating and feeding a plurality of headers 1 to a header transporting assembly 11.