Variable-length to fixed-length conversion of minimum-redundancy codes

Apparatus for converting the code words of variable-length codes into corresponding fixed-length characters, comprising:

• a table storage for storing a first table containing the fixed-length characters and a second table whose contents s(1), s(2), . . . uniquely identify the variable-length code;
• compare/combine circuitry connected to receive successive bits of a code word to be converted into a corresponding fixed-length character;
• summation circuitry connected to said table storage, adapted to respond as said successive code word bits are received to operate on stored elements of said second table to calculate successive values of a weighted sum t(1), t(2), . . . and an unweighted sum b(1), b(2), . . . according to the relation:
• ##EQU8## means connecting said summation circuitry to said compare/combine circuitry;
• means in said compare/combine circuitry responsive to said weighted sum to isolate bits comprising said code word;
• and
• means in said compare/combine circuitry connected to said table storage for adding said code word to said unweighted sum nd subtracting the weighted sum to provide a fixed-length integer for use in indexing said first table.

Apparatus for converting the code words of a variable-length code C.sub.V into corresponding fixed-length characters C.sub.F, comprising:

• a table storage for storing a first table containing the fixed-length characters and a second table whose contents s(1), s(2), . . . uniquely identify the variable-length code;
• compare/combine circuitry connected to receive successive bits y.sub.1, Y.sub.2, . . . of a codeword C.sub.V (i) to be converted into a corresponding fixed-length character;
• summation circuitry connected to said table storage adapted to respond as said successive code word bits are received to operate on stored elements of said second table to calculate successive values of weighted sums t(1), t(2) . . . and unweighted sum b(1), b(2), . . . according to the relations:
• ##EQU9## means connecting said summation circuitry to said compare/combine circuitry;
• means in said compare/combine circuitry responsive to said weighted sum to isolate bits comprising said code word by comparing the successive codeword bits Y.sub.1, Y.sub.2, . . . with successive values of the weighted sum t(1), t(2), . . . until a value t(k) is found to exceed the corresponding k-bit integer
• y(k)=Y.sub.1 Y.sub.2 Y.sub.3 . . . Y.sub.k
• comprising k accumulated codeword bits;
• and
• means in said compare/combine circuitry connected to said table storage for combining said weighted sum and said unweighted sum with said isolated code word to calculate a fixed-length integer i=y(k)-t(k)+b(k) for use in indexing said first table.