US 4,034,199 A · Programmable analog transversal filter

Abstract

A programmable analog transversal filter is disclosed for processing analog signals and comprising a charge-coupled device (CCD) for receiving a series of discrete analog signals to be delayed by increasing periods and applied to the outputs of the CCD, and a plurality of MNOS memory devices coupled to the taps of the CCD and programmed so that the output of a CCD tap is multiplied by a particular factor. In turn, the outputs of the MNOS memory devices are summed to provide an output signal ##EQU1## where W.sub.k is the weighting factor associated the k.sup.th MNOS memory device. The weighting factors are set into the system by varying the threshold voltage of the corresponding MNOS device. Positive and negative weighting factors are implemented by using first and second MNOS memory elements for each tap of the CCD, whereby depending upon the program incorporated into the system, one of the first and second MNOS memory devices is programmed to give either a positive weighting factor and the other MNOS memory device a negative weighting factor. Further, a reiterative method of setting the weights into the MNOS memory device is used to compare the system output indicative of the weighting factor as set into the MNOS memory devices, with the desired weighting factor as stored in a suitable storage memory such as a ROM, whereby a correction signal is developed to adjust the threshold voltage V.sub.Th of the MNOS memory device in accordance with the stored weighting factor. In one illustrative embodiment, the weighting factors are set in accordance with sinusoidal signals, whereby the system performs a filtering function to provide an output upon receipt of an input signal of desired frequency. In addition, the MNOS devices are reprogrammable, thus permitting a single such system to be used in many different applications. In this regard, this system is particularly adapted for complex signal processing including filtering, generating desired functions, synthetic aperture radar signal processing and target identification processing.

Claims17

Dependent claims

A discrete analog signal processing system for processing an analog input signal in accordance with a pattern of weighting factors, said system comprising:

(a) a plurality of memory elements, each capable of storing an analog weighting factor of the pattern and responsive to a portion of the input signal applied thereto for providing an element output indicative of the product of the stored weighting factor and an input signal applied thereto;
(b) an output conductor coupled to receive the element outputs of each of said memory elements;
(c) converter means comprising a plurality of stages, each coupled to corresponding memory elements and responsive to an input signal for disposing sequentially portions of the input signal at each of its stages, whereby a signal portion is applied from its stage to its corresponding memory element;
(d) means for providing a programming signal for a selected memory element corresponding to the weighting factor to be stored therein;
and
(e) register means comprising a plurality of stages corresponding to those of said converter means for deriving sequentially from said register means an enabling output for permitting the application of the programming signal successively to each of said memory elements whereby each of said memory elements is programmed with its corresponding weighting factor.

3 more elements

A discrete analog signal processing system for processing an input signal in accordance with a pattern of weighting factors, said system comprising:

(a) a matrix of memory elements disposed in rows and columns, each of said memory elements comprises an MNOS field effect transistor and capable of storing an analog weighting factor of the pattern and responsive to a portion of the input signal applied thereto for providing an element output indicative of the product of the stored weighting factor and the input signal portion, said matrix further comprising first sets of row and column conductors coupled to the corresponding memory elements of said matrix and means for isolating one row of said memory elements from the remaining rows thereof;
(b) first converter means comprising a plurality of stages, each coupled to corresponding column conductors and responsive to the input signal for disposing sequentially a portion of the input signal at each of its stages, whereby a signal portion is applied through its corresponding column conductor to those memory elements of that column;
(c) second converter means comprising a plurality of stages, each coupled to a row conductor of said matrix, for summing and storing the element outputs of those memory elements of that row and operative to sequentially read out the plurality of summed row signals;
and
(d) means for programming the pattern of weighting factors onto corresponding ones of said memory elements, said programming means including first generator means for applying programming signals to each of said row regions, a second set of column conductors coupled to the gate electrodes of said memory element of that column, and second generator means for applying programming signals to each of said column conductors of said second set.

2 more elements

A discrete analog signal processing system for processing an input signal in accordance with a pattern of weighting factors, said system comprising:

(a) a matrix of memory elements disposed in rows and columns, each of said memory elements capable of storing an analog weighting factor of the pattern and responsive to a portion of the input signal applied thereto for providing an element output indicative of the product of the stored weighting factor and the input signal portion, said matrix further comprising first sets of row and column conductors coupled to the corresponding memory elements of said matrix;
(b) first converter means comprising a plurality of stages, each coupled to corresponding column conductors and responsive to the input signal for disposing sequentially a portion of the input signal at each of its stages, whereby a signal portion is applied through its corresponding column conductor to those memory elements of that column, said first converter means comprises a charge-transfer device (CTD) including a plurality of cells sequentially aligned along the length of said CTD, each of said cells having a plurality of wells formed therein whereby the input signal portions are transferred from cell to cell along the length of said CTD, selected of said cells having output means associated with one of its wells;
(c) second converter means comprising a plurality of stages, each coupled to a row conductor of said matrix, for summing and storing the element outputs of those memory elements of that row and operative to sequentially read out the plurality of summed row signals;
and
(d) means for applying a programming signal to each of said memory elements whereby the analog weighting factor is stored therein.

2 more elements

A discrete analog signal processing system for processing an input signal in accordance with a pattern of weighting factors, said system comprising:

(a) a matrix of memory elements disposed in rows and columns, each of said memory elements capable of storing an analog weighting factor of the pattern and responsive to a portion of the input signal applied thereto for providing an element output indicative of the product of the stored weighting factor and the input signal portion, said matrix further comprising first sets of rows and column conductors coupled to the corresponding memory elements of said matrix;
(b) first converter means comprising a plurality of stages, each coupled to corresponding column conductors and responsive to the input signal for disposing sequentially a portion of the input signal at each of its stages, whereby a signal portion is applied through its corresponding column conductor to those memory elements of that column;
(c) second converter means comprising a plurality of stages, each coupled to a row conductor of said matrix, for summing and storing the element outputs of those memory elements of that row and operative to sequentially read out the plurality of summed row signals;
(d) programming generator means for applying conductance programming signals to each of said memory devices for storing therein a weighting factor in accordance with the pattern of weighting factors;
(e) means for applying a test signal to a selected one of said memory elements, whereby a memory element output is derived indicative of the weighting factor of said selected memory element;
and
(f) comparator means responsive to the memory element output indicative of the weighting factor programmed on said selected memory element for comparing same with a reference value of the weighting factor for said selected memory element to derive an error signal for adjustably controlling said programming generator means to apply program signals to said selected memory element, whereby the weighting factor stored therein is adjusted in accordance with the error signal.

4 more elements

Dependencies are inferred from the claim text.

Programmable analog transversal filter

Life of this patent

Programmable analog transversal filter

Life of this patent

Abstract

Claims17