Process for fabricating narrow polycrystalline silicon members
AssigneeIntel Corporation
InventorWilliam H. Owen, III
Life of this patent
Estimating the term…
Abstract
A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.
Claims14
A process for fabricating a polycrystalline silicon structure from a layer of polycrystalline silicon comprising the steps of:
- forming a masking means on said polycrystalline silicon layer which exposes a line on said polycrystalline silicon layer delineated by an edge or periphery of said masking means;
- doping a region of said polycrystalline silicon layer which includes said line on said layer, the dopant being introduced through said line such that said line acts as a line source for said dopant and such that the width of said region is a function of the extent of said doping and substantially independent of the width of said line, whereby said doped region is adjacent to undoped portions of said polycrystalline silicon layer;
- removing said masking means;
- subjecting said polycrystalline silicon layer to an etchant which discriminates between doped and undoped silicon such that undoped silicon is etched;
- whereby a structure is fabricated from said polycrystalline silicon layer where the critical dimensions of said structure are substantially controlled by the extent of said doping introduced at said line, rather than the masking tolerances.
A process for forming a polycrystalline silicon member from a polycrystalline silicon layer comprising the steps of:
- forming a masking means on said silicon layer, said masking means defining a gap which communicates with said silicon layer, said gap defined by an edge of said masking means;
- diffusing an impurity into said silicon layer through said gap to define a doped region in said silicon layer, the width of said doped region being substantially determined by the extent of said diffusion and substantially independent of the width of said gap;
- removing said masking means;
- selectively etching said silicon layer such that silicon surrounding said doped region is removed;
- whereby said doped region forms a polycrystalline silicon member.
A process for fabricating a polycrystalline silicon structure from a polycrystalline silicon layer comprising the steps of:
- forming a masking member on said silicon layer;
- forming a masking layer on said silicon layer at least adjacent to one edge of said masking member;
- subjecting said masking member and masking layer to a etchant so as to etch said masking member or masking layer to form a gap between an edge of said masking member and said masking layer;
- doping a region of said silicon layer through said gap, the width of said region being substantially determined by the extent of said doping and being substantially independent of the width of said gap;
- removing said masking member and said masking layer;
- etching said silicon layer such that said doped region remains, thereby forming a polycrystalline silicon structure;
- whereby a polycrystalline silicon structure may be formed where the critical dimensions of said structure are controlled by doping and are not substantially dependent on masking tolerance.
Dependencies are inferred from the claim text.