Chip structure

Abstract

A chip counter for use in gaming applications and the like comprising a tray having a trough for receiving chips, which trough is provided with a slit at the bottom thereof. The chips are stacked in the trough and are each provided with a strip about their periphery which is adapted to be more reflective to illuminating light than the main body of the chip. Reading means scans the chips in the trough along the slit provided therefor and counts pulses representative of the passage across the more highly light emissive edge of the chip. The more highly light emissive portions of the edges of each chip are made narrower than the thickness of each chip to develop discrete pulses. Counting of chips of different denominations is accomplished by providing light emissive strips which emit light of differing wavelengths when light activated. The reader employs filters for passing predetermined light wavelength ranges to develop pulses representative of the proper wavelengths of light to make denominational decisions.

Dependencies are inferred from the claim text.