US 4,025,902 AGranted

General purpose sequence controller

AssigneeToyoda Koki Kabushiki Kaisha

InventorsHisaji Nakao, Katutoshi Naruse, Kazuhiko Hasegawa, Sadao Kawade, Yasufumi Tokura, Kazuo Matsuno

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Abstract

A general purpose sequence controller wherein a schematic electric circuit diagram comprising a ladder network of circuit lines disposed between two vertical bus lines is changeable and simulated by a special purpose control program. A logic operation circuit comprises first and second circuit means for examining an external input signal in accordance with examine commands of logical AND and OR functions, respectively, first and second memory means for temporarily memorizing the examined results of the first and second circuit means, respectively, third memory means for temporarily memorizing the application of the examine command of the logical OR function, and identifying circuit means for identifying the examined results of the logic operations in accordance with the contents of the first, second and third memory means.

Claims8

Dependent claims

A programmable sequence controller comprising:

first memory means for memorizing a sequence program comprising a train of instructions, each instruction including an examine command and address information;
input circuit means operatively connected to a plurality of addressed external input devices for converting states of the external input devices into logical values;
output circuit means operatively connected to a plurality of addressed external output devices to be energized or deenergized;
a logic operation circuit operatively connected to the input and output circuit means;
reading means operatively connected to the first memory means, the input and output circuit means and the logic operation circuit for reading out the train of instructions memorized in the first memory means and applying an examine command to the logic operation circuit and address information to one of the input and output circuit means to specify one of the external input and output devices;
the logic operation circuit comprising:
first gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical AND function;
second memory means operatively connected to the first gate means for memorizing a comparison result of the first gate means;
second gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical OR function;
third memory means operatively connected to the second gate means for memorizing a comparison result of the second gate means;
and
identifying circuit means operatively connected to the second and third memory means for identifying the comparison results of the first and second gate means in accordance with the contents of the second and third memory means;
the output circuit means being operatively connected to the identifying circuit means and operable to energize or deenergize one of the addressed external output devices in response to an output of the identifying circuit means in the logic operation circuit.

10 more elements

A programmable sequence controller comprising:

first memory means for memorizing a sequence program comprising a train of instructions, each instruction including an examine command and address information;
input circuit means operatively connected to a plurality of addressed external input devices for converting states of the external input devices into logical values;
output circuit means operatively connected to a plurality of addressed external output devices to be energized or deenergized;
a logic operation circuit operatively connected to the input and output circuit means;
reading means operatively connected to the first memory means, the input and output circuit means and the logic operation circuit for reading out the train of instructions memorized in the first memory means and applying an examine command to the logic operation circuit and address information to one of the input and output circuit means to specify one of the external input and output devices;
the logic operation circuit comprising:
first gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical AND function;
second memory means operatively connected to the first gate means for memorizing a comparison result of the first gate means;
second gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical OR function;
third memory means operatively connected to the second gate means for memorizing a comparison result of the second gate means;
and
a logic transfer circuit operatively connected to the second and third memory means for transferring the content of the third memory means to the second memory means at the end of a comparison of a logical value with the final examine command among a group of successively read out examine commands for a logical OR function;
the output circuit means being operatively connected to the logic transfer circuit and operable to energize or deenergize one of the addressed external output devices in response to an output of the second memory means in the logic operation circuit.

10 more elements

A programmable sequence controller comprising:

first memory means for memorizing a sequence program comprising a train of instructions, each instruction including an examine command and address information;
input circuit means operatively connected to a plurality of addressed external input devices for converting states of the external input devices into logical values;
output circuit means operatively connected to a plurality of addressed external output devices to be energized or deenergized;
a logic operation circuit operatively connected to the input and output circuit means;
reading means operatively connected to the first memory means, the input and output circuit means and the logic operation circuit for reading out the train of instructions memorized in the first memory means and applying an examine command to the logic operation circuit and address information to one of the input and output circuit means to specify one of the external input and output devices;
the logic operation circuit comprising:
first gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical AND function;
second memory means operatively connected to the first gate means for memorizing a comparison result of the first gate means;
second gate means operatively connected to the input circuit means and the reading means for comparing a logical value of the external input device specified by address information with a condition specified by an examine command for a logical OR function;
third memory means operatively connected to the second gate means for memorizing a comparison result of the second gate means;
fourth memory means operatively connected to the reading means for memorizing an application of the examine command for a logical OR function;
and
identifying circuit means operatively connected to the second, third and fourth memory means for identifying the comparison results of the first and second gate means in accordance with the contents of the second, third and fourth memory means;
and
the output circuit means being operatively connected to the identifying circuit means and operable to energize or deenergize one of the addressed external output devices in response to an output of the identifying circuit means in the logic operation circuit.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/479,039Filed 13 Jun 1974 · continuation
Priority: JA 47-7672131 Jul 1972
Granted: 24 May 1977
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G05B 19/05
Program control other than numerical control, i.e. in sequence controllers or logic controllers: programmable logic controllers, e.g. simulating…
G05B 2219/13128
Plc programming: relay ladder diagram, RLL RLD KOP
G05B 2219/15105
Plc structure of the system: hardwired logic to accelerate, speed up execution of instructions
G05B
Control or regulating systems in general