Signal amplifier circuit using a pair of complementary junction field effect transistors

A signal amplifier circuit comprising:

• an amplifier input to receive an input signal to be amplified;
• an amplifier output to derive an amplified signal therefrom;
• a first power supply terminal for applying a first D.C. electrical potential;
• a second power supply terminal for applying a second D.C. electrical potential;
• a complementary pair of first and second junction field effect transistors coupled in series in a source-to-source relationship between said first power supply terminal and said second power supply terminal, the gate electrode of said first transistor being coupled to said amplifier input;
• a first load impedance means coupled between said second transistor and said second power supply terminal;
• a complementary pair of third and fourth junction field effect transistors coupled in series in a source-to-source relationship between said first and second power supply terminals, said fourth transistor being complementary to said first transistor, the gate electrode of said fourth transistor being coupled to the junction of said second transistor and said first load impedance means, and the drain electrode of said third transistor being coupled to said amplifier output;
• a second load impedance means coupled between said third transistor and said first power supply terminal;
• and
• biasing means coupled to said first and second power supply terminals for applying a D.C. potential to the gate electrode of each of said first, second and third transistors.

A signal amplifier circuit comprising:

• an amplifier input to receive an input signal to be amplified;
• an amplifier output to derive an amplified signal therefrom;
• a first power supply terminal for applying a first D.C. electrical potential;
• a second power supply terminal for applying a second D.C. electrical potential;
• a complementary pair of first and second junction field effect transistors coupled in series in a source-to-source relationship between said first power supply terminal and said second power supply terminal, the gate electrode of said first transistor being coupled to said amplifier input;
• a first load impedance means coupled between said second transistor and said first power supply terminal;
• a complementary pair of third and fourth junction field effect transistors coupled in series in source-to-source relationship between said first and second power supply terminals, said third transistor being complementary to said second transistor, the gate electrode of said third transistor being coupled to the junction of said second transistor and said first load impedance means, and the drain electrode of said fourth transistor being coupled to said amplifier output;
• a second load impedance means coupled between said fourth transistor and said first power supply terminal;
• and
• biasing means coupled to said first and second power supply terminals for applying a D.C. potential to the gate electrode of each of said first, second and fourth transistors.