Programmable arrays
OwnerFrank Manninginventor
Life of this patent
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Abstract
Iterative units of an array are programmed for selected processing functions, for unit testing, and for avoidance of defective units, by loading mechanisms which permit a unit to be programmed and then to extend a loading path to an adjacent unit, so that loading paths may be established directly from unit to unit, with the loaded units serving as wires to transmit loading information to a unit to be loaded. After loading, the loading paths may be retracted (disconnected) leaving the loaded units in condition for the performance of desired processing functions. For example, the loaded units may form one or more shift registers, may serve as wires for transmitting test signals to and from a unit to be tested, and may be arranged to avoid defective units.
Claims27
An array comprising iterative units in which each of said units includes memory means, plural input and output means, means for storing information in the memory means from selected input means, means dependent upon the information stored in said memory means for selecting output means, and means for transmitting information from selected input means through said unit to the selected output means, each iterative unit having particular output means uniquely connected to particular input means of other predetermined iterative units discretely, whereby the selection of a particular output means of a unit permits the transmission via that unit of information to be stored in a selected discrete other unit.
An array comprising iterative units in which each of said units includes memory means, plural input and output means, means for storing information in the memory means from selected input mans, means dependent upon the information stored in said memory means for selecting output means, and means for transmitting information from selected input means through said unit to the selected output means, each iterative unit having particular output means connected to particular input means of other predetermined iterative units, whereby the selection of a particular output means of a unit permits the transmission via that unit of information to be stored in a selected other unit, said memory means including a plurality of registers, one of which has means for selecting the output means of the cell and has means for selecting the input means connected to another register, each unit having means for initializing said one register's condition and means for terminating the storage of information therein.
In an array of iterative units having means for storing information, means for loading information into a selected unit, and means in the loaded unit responsive to said loading for selecting uniquely a discrete another unit to be loaded through the loaded unit, each selected unit having means for selecting uniquely another discrete unit to be loaded therethrough.
An array according to claim 19, wherein said disconnecting means includes means to disconnect said units incrementally from said tip.
A method of forming a system from selected units of an array, comprising storing information in a first selected unit, uniquely selecting in response to the stored information a discrete second unit for receiving information via the first selected unit, and transmitting information to the second unit via the first unit.
A method of establishing and testing signal paths in an array of programmable iterative units, comprising programming certain units to serve as an input wire and an output wire, programming a unit to serve as a loop connecting the input and output wires, and testing the continuity of the signal path including the input wire, the loop, and the output wire.
An array comprising machine units in which each of said units has plural input and output sets with each such set connected, if at all, uniquely to a discrete unit or an extra-array machine, means for determining whether an input set is input-activated, means for storing information input from said input-activated set, means responsive to information stored to output-activate and output set, and means for subsequently transmitting information from the input-activated set to the output-activated set.
An array comprising iterative units in which each of said units includes memory means, plural input and output means, means for storing information in the memory means from selected input means, means dependent upon the information stored in said memory means for selecting output means, and means for transmitting information from selected input means through said unit to the selected output means, each iterative unit having particular output means connected to particular input means of other predetermined iterative units, whereby the selection of a particular output means of a unit permits the transmission via that unit of information to be stored in a selected other unit, said connection of particular output means to particular input means providing signal lines and there being no signal lines connecting more than two units.
Dependencies are inferred from the claim text.