Interpolation-decimation circuit for increasing or decreasing digital sampling frequency
AssigneeBell Telephone Laboratories, Incorporated
InventorsRonald Eldon Crochiere, Lawrence Richard Rabiner
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Abstract
A general purpose interpolator-decimator circuit for increasing or decreasing the sampling rate of a digital signal by a factor L/M, where L and M are integers, is disclosed. The circuit includes means for determining each output sample by multiplying a sequence of previous input samples by a set of coefficients and accumulating the resulting products. L sets of coefficients, in which each coefficient is a function of the factors L and M, are stored in a specific sequence which permits sequential addressing of both the coefficients and input signal samples. A multistage decimator cascaded with a multistage interpolator to effect a narrow-band FIR filter is also disclosed.
Claims9
Apparatus for converting the sampling rate of a digital input signal from f.sub.r to (L/m) )f.sub.r, where L and M are integers, comprising
- means for storing Q consecutive samples of said input signal where Q is a predetermined integer;
- multiplier means having first and second input terminals for supplying an output signal which is the product of the signals applied to said first and second input terminals;
- coefficient storage means for storing L sets of coefficients, g.sub.i (n), i=0, 1, . . . , (L-1), each of said L sets of coefficients having Q elements with the k.sup.th element, k=0, 1, . . . , (Q-1), equal to g.sub.i (k) = h(kL + (iM) modules L), where the function h denotes the coefficients of a direct form FIR filter with unit sample response length N and;
- sequence means for sequentially transferring each coefficient set g.sub.i (n) to said first multiplier input terminal and sequentially transferring each of said consecutive Q input samples to said second multiplier input terminal;
- and
- accumulation means for summing the products supplied by multiplier means over the range k=0 to k=Q-1.
Apparatus for converting an applied digital signal with a sampling rate of f.sub.r to an output signal comprising a series of output samples y(n) at a sampling rate (L/M)f.sub.r, where L and M are different integers, comprising:
- means for storing a set of Q input signal samples ##EQU5## where Q is a predetermined integer and the expression (nM/L) denotes the next largest integer portion of the quantity included therein;
- multiplier means responsive to first and second multiplier input signals for forming the product thereof;
- coefficient storage means for storing L sets of coefficients g.sub.i (n), i=0, 1, . . . ,(L-1), each set of coefficients including Q elements with the k.sup.th element, g.sub.i (k), k=0, 1, . . . ,(Q-1) equal to [g.sub.i (k) =] h(kL + (iM) module L)
- first sequencing means for sequentially and cyclically selecting consecutive coefficient sets;
- second sequencing means for simultaneously supplying the k.sup.th element of said selected set of coefficients and the k.sup.th stored input sample as said first and second multiplier input signals;
- means for accumulating the products formed by said multiplier means over the range k=0 to k=(Q-1) to form said output signal sample y(n);
- and
- means for updating said means for storing said input samples with the input signal samples which occur within a time period of M/(Lf.sub.r) after said input sample x(nM/L).
Apparatus for converting a sampled data input signal having a sampling rate f.sub.r to a sampled data output signal having a sampling rate (L/M)f.sub.r comprising:
- storage means for storing a sequence of Q input signal samples, ##EQU6## where Q is a predetermined integer, the expression (nM/L) denotes the integer portion of the quantity thereby enclosed, and n identifies a particular output sample y(n);
- coefficient storage means for storing L sets of coefficients g.sub.i (k), i=0, 1, . . . ,(L-1), each set of coefficients having Q elements, each set of said coefficients stored in the sequence h(kL+(iM) modulo L), for k=0, 1, . . . (Q-1);
- a multiplier circuit responsive to a single input sample and a single coefficient for forming the product thereof;
- sequencing means for sequentially applying shift signals to said input sample storage means and for sequentially addressing said coefficient storage means to supply said sequence of Q input signal samples and the coefficients of consecutive sets of coefficients of said coefficient storage means to said multiplier circuit;
- accumulator means for determining the output sample y(n) by summing the products supplied by said multiplier means over the range k=0 to k=(Q-1);
- means for updating said input sample storage means by ##EQU7## samples;
- and means connected to said sequencing means for incrementing n by one unit so that said sequencing means, said multiplier means, and said accumulator means sequentially determine each output sample y(n), y(n+1), y(n+2), . . .
Dependencies are inferred from the claim text.