Conditional latch circuit

A logic circuit comprising, in combination:

• Or gate means having first, second and third inputs and an output;
• first AND gate means having fourth and fifth inputs and an output;
• second AND gate means having sixth and seventh inputs and an output;
• third AND gate means having eighth and ninth inputs and an output;
• fourth AND gate means having tenth and eleventh inputs and an inverted output and a non-inverted output;
• means connecting the outputs of said first, second and third AND gate means to respective ones of said first, second and third inputs;
• means connecting said inverted output of said fourth AND gate means to said fourth and sixth inputs;
• means connecting said non-inverted output of said fourth AND gate means to said eighth input;
• means connecting said output of said OR gate means to said ninth input;
• and
• means connecting a binary clock pulse signal having a first binary value to said tenth input,
• whereby upon application of a signal having said first binary value to said eleventh input, said circuit operates as an OR gate to signals of a second binary value appearing at either of said fifth and seventh inputs, and whereby upon application of a signal having said second binary value to said eleventh input, said circuit operates as a storage means to store signals of a second binary value appearing at either of said fifth and seventh inputs;
• said second binary value being different from said first binary value;
• and said output of said OR gate means providing the output of said circuit.