Stacked logic design for I.sup.2 L watch
AssigneeTexas Instruments Incorporated
InventorClark R. Williams
Life of this patent
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Abstract
An electronic timekeeping system is implemented in bipolar integrated circuit technology for displaying time by way of a digital display. The bipolar circuitry is implemented utilizing integrated injection logic and is interconnected with a plurality of circuit elements connected in parallel in levels such that the levels are electrically stacked and serially diode coupled.
Claims14
A digital system in the form of a monolithic semiconductor integrated circuit which is energizable from a single power source of predetermined magnitude connected between first and second terminals thereof, said system comprised of:
- a. first and second logic levels each having at least one logic input and at least one logic output, each of said logic levels being comprised of a plurality of interconnected logic elements with each of said logic elements being comprised of semiconductor devices and having first and second power electrodes for energization thereof;
- b. first means coupling the first power electrodes of the logic elements of said first level in common to said first terminal;
- c. second means electrically coupling the second power electrodes of the logic elements of said second level in common to said second terminal;
- d. third means electrically coupling the second electrodes of the logic elements of said first level in common to the first electrodes of the logic elements of the second level;
- and
- e. a PN junction device coupling the at least one logic output of said first level to the at least one logic input of said second level.
A digital system in the form of a monolithic semiconductor integrated circuit which is energizable from a single power source of predetermined magnitude connected between first and second terminals thereof, said system comprised of:
- a. N cascaded logic levels each having at least one logic input and at least one logic output and being comprised of a plurality of electrically interconnected logic elements;
- b. each of said logic elements being comprised of one or more pairs of bipolar semiconductor transistors and having first and second power electrodes for energization thereof;
- c. a first transistor of each pair being coupled between said first and second electrodes for providing driving current to the second transistor of the pair;
- d. the first power electrodes of the logic elements of a first of said N levels coupled in common to said first terminal;
- e. the second power electrodes of the logic elements of the N.sup.th level coupled in common to said second terminal;
- f. the second power electrodes of the logic elements of the first to (N-1).sup.th levels respectively coupled in common to the first power electrodes of the logic elements of the second to N.sup.th levels respectively coupled in common;
- and
- g. PN junction devices coupling the at least one logic outputs of said first to (N-1).sup.th levels respectively to the at least one logic inputs of said second to N.sup.th levels.
Dependencies are inferred from the claim text.