High density CMOS process
AssigneeIntel Corporation
InventorsEdward J. Boleky, Charles Scott
Life of this patent
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Abstract
A process for fabricating high density, high voltage CMOS devices. The process provides self-aligning, full channel stops which are formed prior to the fabrication of the active devices. The aligned full channel stops and a well are formed in the substrate without intermediate masking.
Claims20
On a silicon substrate which includes a first area for a first MOS device and a second spaced-apart area for a second MOS device, a process for forming channel stops of opposite conductivity type in the intermediate region between said first and second areas, comprising the steps of:
- forming a masking member on said substrate, said masking member protecting a portion of said intermediate region;
- doping the portion of said intermediate region unprotected by said masking member with a dopant of a first conductivity type to define a first channel stop;
- removing said masking member;
- doping said intermediate region with a dopant of a second conductivity type forming a second channel stop adjacent to said first channel stop;
- whereby adjacent full channel stops may be fabricated in alignment with each other and with said first and second areas.
A process for fabricating CMOS devices on a silicon substrate comprising the steps of:
- defining a spaced-apart first area and second area on said substrate wherein at least the intermediate area between said first and second areas is covered with a protective layer;
- forming a masking member on said protective layer said masking member covering said second area and extending from said second area partway onto said intermediate area;
- ion implanting said first area with a dopant of a first conductivity type;
- removing portions of said protective layer employing said masking member as a mask, such that at least said protective layer adjacent to said first area is removed;
- doping said substrate adjacent to said first area with a dopant of said first conductivity type to form a first channel stop of said first conductivity type;
- removing at least said masking member;
- doping said intermediate area with a dopant of a second conductivity type thereby forming a second channel stop of said second conductivity type;
- fabricating active devices in said substrate at said first and second areas;
- whereby full channel stops are fabricated which are in alignment with one another and in alignment with said active devices.
On a silicon substrate which includes a first area for a first MOS device and a second spaced-apart area for a second MOS device, a process for forming channel stops of opposite conductivity type in the intermediate region between said first and second areas, comprising the steps of:
- doping said intermediate region with an impurity of a first conductivity type to define a first channel stop of a first conductivity type;
- forming a masking member on said substrate, said masking member protecting a portion of said intermediate region;
- doping the unprotected portion of said intermediate region of said silicon substrate with a dopant of a second conductivity type to define a second channel stop of a second conductivity type;
- whereby full channel stops may be fabricated in alignment with each other and with said first and second areas.
Dependencies are inferred from the claim text.