Switching arrangement for transmitting data in time division multiplex systems

Abstract

A switching arrangement is described for transmitting data in time division multiplex (TDM) systems on a character frame basis. The system includes a polarity reversal recognition circuit producing a polarity reversal signal and signaling polarity reversals of a data signal. A blocking circuit arrangement produces a stop signal thereby blocking the polarity reversal recognition circuit throughout the duration of a predetermined number of m bits of the data signal. A clock generator produces a clock signal which facilitates the sampling of the data signal. A shift register is provided which contains no fewer than m+2 cells and has a set of parallel input terminals for the parallel coupling of binary digits to the shift register. Serial input terminals to the shift register provide for the serial application of binary digits to the shift register. A clock pulse input terminal to the shift register receives shift register clock pulses. A gate is provided for receiving the polarity reversal signal and the output signal of the last cell of the shift register. The output from the foregoing gate yields a phase position signal which is utilized to determine the phase position of the clock signal which is applied to the aforementioned clock pulse input terminal of the shift register. The output signal of the second to last cell of the shift register is applied as a stop signal to the polarity reversal recognition circuit. The phase position signal is coupled to two or more parallel input terminals of the shift register. The serial input terminals of the shift register receive binary digits differing from the binary digits of the phase position signal that are applied to the parallel input terminals of the shift register.

Dependencies are inferred from the claim text.