Transistor circuits
AssigneeRCA Corporation
InventorLeonard Robert Salvatore
Life of this patent
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Abstract
A circuit and method for indicating the rise time in switching a transistor on, and the fall time in switching the transistor off. A voltage is produced indicative of the transistor collector current and this voltage is compared with first and second reference voltage levels indicative of 10% and 90% of the maximum collector current. To measure rise time, a pulse counter is started when the 10% level is reached and stopped when the 90% level is reached. To measure fall time, a second pulse counter is started when the 90% level is reached and stopped when the 10% level is reached.
Claims7
A transistor test circuit for measuring the time required for the current passing through the conduction path of a transistor to pass from a first to a second value when the transistor is switched from a nonconducting to a conducting state and for measuring also the time required for this current to pass from the second to the first value when the transistor is switched from its conducting to its nonconducting state comprising, in combination:
- means for translating said current to a voltage proportional thereto;
- means for providing first and second reference voltage levels indicative of said first and second values, respectively, of said current;
- comparator means respective of said first and second voltage levels and of said voltage proportional to current for producing a first signal manifestation in response to said voltage being lower than said first level, a second signal manifestation in response to said voltage reaching said first level, and a third signal manifestation in response to said signal reaching said second level;
- first and second counter means, each for counting at a given rate when turned on;
- means for providing clock signal pulses;
- And gate means having at least one input terminal receptive of said clock signals;
- and
- means responsive to the order of occurrence of said first, second, and third signal manifestations, for priming said AND gate means to deliver clock pulses to said first counter, whenever said second signal manifestation follows said first signal manifestation, and thereafter disabling said AND gate means when said third signal manifestation is attained, and for priming said AND gate means to deliver pulses to said second counter, whenever said second signal manifestation follows said third signal manifestation, and thereafter disabling said AND gate means when said first signal manifestation is attained.
Dependencies are inferred from the claim text.