Implementation of surface sensitive semiconductor devices

Abstract

A semiconductor structure is disclosed which reliably provides for very high PN junction reverse breakdown voltages. A very high resistivity film overlying a junction-protecting oxide passivation layer and making electrical contact with the P-type material and the N material of the subject PN junction is utilized to neutralize the effects of accumulated charge on or within the oxide passivation layer. Annular guard rings surrounding and spaced from the subject PN junction may be biased by contacting the high resistivity film, thereby improving the PN junction reverse breakdown voltage. The stability of the shunt leakage current through the high resistivity film is greatly increased by means of a thin, high integrity oxide layer grown or deposited thereon. In integrated circuit structures, parasitic FET paths due to inversion of semiconductor material caused by charge accumulations at the oxide surface are suppressed by judicious electroding, wherein the oxide surface potential over critical regions is set to desired values by judicious extensions of interconnnect metalization and very high resistivity films over the oxide surface, and in intimate contact therewith. The use of the very high resistivity film allows setting of oxide surface potentials over critical areas otherwise unaccessible because of metal interconnect layout limitations.

Dependencies are inferred from the claim text.