US 4,007,384 AGranted

Noninverting current-mode logic gate

AssigneeBell Telephone Laboratories, Incorporated

InventorRichard Donald Brooks

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Abstract

A high speed bipolar noninverting current-mode logic AND gate is the basic building block for a current-mode logic family. The AND gate comprises a current steering differential pair of transistors, a pair of dual emitter input transistors, a dual emitter reference transistor, an output resistor and a fixed current source. The conducting state of the current steering transistor pair is so controlled that a logic "one" at the base electrodes of both input transistors produces a logic "one" at an output terminal taken from the collector electrode of the reference transistor. Further, a logic "zero" at both input transistors produces a logic "zero" at the output terminal and finally the condition of a "zero" at one input and a "one" at the other input produces a "zero" at the output. This result is attained as a consequence of control of the conduction state of the current steering pair so as to provide the same current level through the reference transistor for the "zero-one" input as for the "zero-zero" input, thus producing the noninverting AND function.

Claims3

Dependent claims

A noninverting current-mode logic AND gate comprising,

1. a pair of input terminals,
2. an output terminal,
3. a source of substantially constant current, including a supply terminal adapted for connection to a source of voltage,
4. a pair of differentially-connected, emitter-coupled, current steering transistors connected to said current source,
5. a first input transistor having its base connected to one of said input terminals,
6. a second input transistor having its base connected to the other input terminal,
7. said input transistors having dual emitters,
8. a reference transistor having its collector connected to said output terminal and having dual emitters,
9. first means connecting one emitter of said first input transistor to one emitter of said reference transistor and to the collector of one of said current steering transistors,
10. second means connecting one emitter of said second input transistor to the other emitter of said reference transistor and the other collector of the other of said current steering transistors,
11. third means connecting the other emitter of said first input transistor to the base electrode of the other of said current steering transistors, and
12. fourth means connecting the other emitter of said second input transistor to the base electrode of said one of the current steering transistors.

9 more elements

Dependencies are inferred from the claim text.