Switching transient suppression circuit
AssigneeUnited Technologies Corporation
InventorJohn H. Tomlinson
Life of this patent
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Abstract
A circuit responsive to a change in the state of a switch for suppressing spurious electrical pulses associated with switch contact opening and closing. The suppression circuit includes a dual Schmitt trigger having its individual trigger circuits connected in series and having the input of the first trigger stage clamped to a first output of the first trigger stage to delay firing of the trigger circuits until switching transients have subsided. The dual trigger is provided with an output disable input whereby outputs of the series connected trigger circuits may be caused to assume a high resistance state thereby permitting a plurality of the suppression circuits to be connected between input switches and a common logic bus.
Claims9
A circuit responsive to the change in state of a switch for suppressing spurious electrical pulses associated with switch contact opening and closing comprising:
- trigger circuit means, said trigger circuit means including a pair of series connected Schmitt trigger circuits, said trigger circuits each having an input terminal and a pair of output terminals, a first output of each of said trigger circuits having the capability of assuming either of two logic states or a high resistance state, said trigger circuit means having an output disable input which may be employed to cause the first outputs of the trigger circuits to assume the high resistance state;
- means for delivering a signal commensurate with the state of a switch to the input terminal of the first of said series connected trigger circuits of said trigger circuit means;
- means for connecting the first output terminal of the second of said series connected trigger circuits of said trigger circuit means to a logic output bus;
- means for clamping the second output terminal of the first of said trigger circuits of said trigger circuit means to said input terminal of said first of said trigger circuits;
- and
- means for generating and selectively applying a signal to said trigger circuit means output disable input whereby said trigger circuit means will apply to the logic output bus either a logic signal commensurate with the signal delivered to the input terminal of the first of said series connected trigger circuits or will present a high resistance to the logic output bus.
Dependencies are inferred from the claim text.