Arithmetic unit for a digital data processor

An arithmetic unit for performing arithmetic operations with multidigit binary coded numbers in zoned format wherein each multidigit number is comprised of a sequence of M binary bits which is subdivided into alternate N-bit zone fields and N-bit digit fields, such arithmetic unit comprising:

• parallel binary arithmetic circuitry for simultaneously arithmetically combining two M-bit binary bit sequences to produce an output M-bit binary bit sequence representing the results of the arithmetic operation;
• first modifier circuitry for receiving a first M-bit multidigit zoned binary coded number and causing any nonzero bits in the N-bit zone fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second M-bit multidigit zoned binary coded number and causing any zero bits in the N-bit zone fields thereof to assume a binary value of one and supplying the resulting number to a second input side of the binary arithmetic circuitry;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for producing an output M-bit binary bit sequence wherein the bits in each N-bit zone field position therein have the proper zone code values.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in zoned format wherein each multidigit number is comprised of a sequence of binary bits which is subdivided into alternate four-bit zone fields and four-bit digit fields, such arithmetic unit comprising:

• parallel binary adder circuitry for adding two multibit binary bit sequences to produce an output multibit binary bit sequence representing the sum of the two input bit sequences;
• first modifier circuitry for receiving a first multidigit zoned binary coded decimal number and forcing each bit in the zone fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary adder circuitry;
• second modifier circuitry for receiving a second multidigit zoned binary coded decimal number and forcing each bit in the zone fields thereof to assume a binary value of one and supplying the resulting number to a second input side of the binary adder circuitry;
• and third modifier circuitry coupled to the output side of the binary adder circuitry for receiving the output binary bit sequence produced by the binary adder circuitry and causing the bits in each zone field position therein to assume the proper zone code values.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in zoned format wherein each multidigit number is comprised of a sequence of binary bits which is subdivided into alternate zone fields and digit fields with the zone field adjacent the least significant digit field being used as a polarity-indicating sign field, such arithmetic unit comprising:

• binary arithmetic circuitry for arithmetically combining two multibit binary bit sequences to produce an output multibit binary bit sequence representing the results of the arithmetic operation;
• first modifier circuitry for receiving a first multidigit zoned binary coded decimal number and causing any nonzero bits in the zone and sign fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit zoned binary coded decimal number and causing any zero bits in the zone and sign fields thereof to assume a binary value of one and supplying the resulting number to a second input side of the binary arithmetic circuitry;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for receiving the output binary bit sequence produced by the binary arithmetic circuitry and causing the bits in the sign field position therein to assume proper sign code values and causing the bits in each of the other zone field positions therein to assume the proper zone code values.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in zoned format wherein each multidigit number is comprised of a sequence of binary bits which is subdivided into alternate zone fields and digit fields with the zone field adjacent the least significant digit field being used as a polarity-indicating sign field, such arithmetic unit comprising:

• binary arithmetic circuitry for arithmetically combining two multibit binary bit sequences to produce an output multibit binary bit sequence representing the results of the arithmetic operation;
• first modifier circuitry for receiving a first multidigit zoned binary coded decimal number and causing any nonzero bits in the zone and sign fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit zoned binary coded decimal number and causing any zero bits in the zone and sign fields thereof to assume a binary value of one and including selectively operable complement circuitry capable of complementing the digit fields in the second number, the output of this second modifier circuitry being coupled to a second input side of the binary arithmetic circuitry;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for receiving the output binary bit sequence produced by the binary arithmetic circuitry and causing the bits in the sign field position therein to assume sign code values which indicate the same polarity as indicated by the sign code field of the number received by the first modifier circuitry and causing the bits in each of the other zone field positions therein to assume the proper zone code values.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in zoned format wherein each multidigit number is comprised of a sequence of binary bits which is subdivided into alternate zone fields and digit fields, such arithmetic unit comprising:

• binary arithmetic circuitry for arithmetically combining two multibit binary bit sequences to produce an output multibit binary sequence representing the results of the arithmetic operation;
• first modifier circuitry for receiving a first multidigit zoned binary coded decimal number and causing any nonzero bits in the zone fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit zoned binary coded decimal number and causing any zero bits in the zone fields thereof to assume a binary value of one and supplying the resulting number to a second input side of the binary arithmetic circuitry;
• circuitry included in one of the first and second modifier circuitries for causing the number values in the digit field in the number received by such modifier circuitry to be increased by a factor of six;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for receiving the output binary bit sequence produced by the binary arithmetic circuitry and including circuitry for causing the bits in each zone field position therein to assume the proper zone code values and further including circuitry for receiving digit field carry-out status signals from the binary arithmetic circuitry and circuitry responsive to such status signals for causing the number values in the digit fields of the output binary bit sequence to be decreased by a factor of six for those digit fields for which the corresponding carry-out status signals have a particular carry/no-carry status condition.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in either zoned decimal format or packed decimal format, such arithmetic unit comprising:

• binary arithmetic circuit for arithmetically combining two multibit binary bit sequences to produce an output multibit bit sequence representing the results of the arithmetic operation;
• control signal input circuitry for receiving a format status signal providing a zoned status indication for zoned decimal operation and a packed status indication for packed decimal operation;
• first modifier circuitry for receiving a first multidigit binary coded decimal number and responsive to the format status signal for causing any nonzero bits in the zoned decimal zone and sign field positions to assume a binary value of zero when a zoned status is indicated and for causing any nonzero bits in the packed decimal sign field position to assume a binary value of zero when a packed status is indicated, the output of this first modifier circuitry being coupled to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit binary coded decimal number and responsive to the format status signal for causing any zero bits in the zoned decimal zone and sign field positions to assume a binary value of one when a zoned status is indicated and for causing any zero bits in the packed decimal sign field position to assume a binary value of one when a packed status is indicated, the output of this second modifier circuitry being coupled to a second input side of the binary arithmetic circuitry;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for receiving the output binary bit sequence produced by the binary arithmetic circuitry and responsive to the format status signal for producing an output binary bit sequence wherein the bits in the zoned decimal zone and sign field positions have the proper zone and sign code values when a zoned status is indicated and wherein the bits in the packed decimal sign field position have the proper sign code values when a packed status is indicated.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in either zoned decimal format or packed decimal format, such arithmetic unit comprising:

• binary arithmetic circuitry for arithmetically combining two multibit binary bit sequences to produce an output multibit binary bit sequence representing the results of the arithmetic operation;
• control signal input circuitry for receiving a format status signal providing a zoned status indication for zoned decimal operation and a packed status indication for packed decimal operation;
• first modifier circuitry for receiving a first multidigit binary coded decimal number and responsive to the format status signal for causing any nonzero bits in the zoned decimal zone and sign field positions to assume a binary value of zero when a zoned status is indicated and for causing any nonzero bits in the packed decimal sign field position to assume a binary value of zero when a packed status is indicated, the output of this first modifier circuitry being coupled to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit binary coded decimal number and responsive to the format status signal for causing any zero bits in the zoned decimal zone and sign field positions to assume a binary value of one when a zoned status is indicated and for causing any zero bits in the packed decimal sign field position to assume a binary value of one when a packed status is indicated, the output of this second modifier circuitry being coupled to a second input side of the binary arithmetic circuitry;
• sign control circuitry for detecting the polarities of the numbers supplied to the first and second modifier circuitries and developing a sign control signal;
• and third modifier circuitry coupled to the output side of the binary arithmetic circuitry for receiving the output binary bit sequence produced by the binary arithmetic circuitry and responsive to the format status signal and the sign control signal for producing an output binary bit sequence wherein the bits in the zoned decimal zone and sign field positions have the proper zone and sign code values when a zoned status is indicated and wherein the bits in the packed decimal sign field position have the proper sign code values when a packed status is indicated.

An arithmetic unit for performing arithmetic operations with multidigit binary coded decimal numbers in zoned format wherein each multidigit number is comprised of a sequence of binary bits which is subdivided into alternate zone fields and digit fields with one of the zone fields being used as a sign field to indicate the polarity of the number, such arithmetic unit comprising:

• binary arithmetic circuitry for selectively adding or subtracting two multidigit binary coded decimal numbers;
• first modifier circuitry for receiving a first multidigit zoned binary coded decimal number and causing any nonzero bits in the zone and sign fields thereof to assume a binary value of zero and supplying the resulting number to a first input side of the binary arithmetic circuitry;
• second modifier circuitry for receiving a second multidigit zoned binary coded decimal number and causing any zero bits in the zone and sign fields thereof to assume a binary value of one and supplying the resulting number to a second input side of the binary arithmetic circuitry;
• sign handling circuitry responsive to the sign fields in the two received numbers and to an external selection signal for selecting the arithmetic operation performed by the binary arithmetic circuitry;
• third modifier circuitry coupled to the output side of the binary arithmetic circuitry for producing an output binary bit sequence wherein the bits in each zone field position therein have the proper zone code values;
• and sign control circuitry coupled to the third modifier circuitry and responsive to the sign field in at least one of the received numbers for causing the bits in the sign field position in the output bit sequence to have the proper sign code values.

An arithmetic unit for performing arithmetic operations with positive and negative binary coded decimal numbers each having one or more digit fields representing digit values and a sign field representing the polarity of the number, such arithmetic unit comprising:

• binary adder circuitry for adding two multidigit binary numbers;
• first input circuitry for receiving a first binary coded decimal number and supplying same to a first input side of the binary adder circuitry;
• second input circuitry for receiving a second binary coded decimal number and supplying same to the second input side of the binary adder circuitry;
• plus six/complement circuitry coupled in circuit between the second input circuitry and the second input side of the binary adder circuitry and selectively operable for supplying the second binary coded decimal number to the adder circuitry in either plus six form or complement form;
• sign handling circuitry responsive to the sign fields in the two received numbers and to an external selection signal for controlling the plus six/complement action of the plus six/complement circuitry;
• output circuitry for receiving the output number produced by the binary adder circuitry;
• sign control circuitry coupled to the output circuitry and normally operative to set the sign field in the output number to indicate the same polarity as indicated by the sign field of the number received by the first input circuitry;
• complement detector circuitry for determining whether the output number is in complement form;
• and circuitry operable in the event that the output number is in complement form for supplying such output number back to the second input circuitry, for causing the plus six/complement circuitry to complement such number, for causing the adder circuitry to add the resulting complemented number to a first input circuitry number value of zero and for causing the sign control circuitry to set the sign field in the resulting adder circuitry output number to indicate a polarity opposite to the polarity of the original output number.

In an arithmetic unit having arithmetic circuitry for selectively adding or subtracting first and second numerical operands each having a plural bit sign field encoded to represent the polarity of the operand and wherein there are plural codes for each of the positive and negative polarities, automatic sign handling circuitry comprising:

• first sign code detector circuitry for decoding the plural-bit sign field of the first operand for producing a polarity signal indicating the polarity of the first operand;
• second sign code detector circuitry for decoding the plural-bit sign field of the second operand for producing a polarity signal indicating the polarity of the second operand;
• circuitry for receiving a further polarity signal indicating whether the requested arithmetic operation is addition or subtraction;
• a first exclusive OR circuit responsive to two of the polarity signals for producing an intermediate signal;
• and a second exclusive OR circuit responsive to the intermediate signal and to the third polarity signal for producing a control signal for controlling the arithmetic operation actually performed by the arithmetic circuitry.

In an arithmetic unit having arithmetic circuitry for selectively adding or subtracting first and second binary coded decimal operands in either zoned or packed format wherein each operand includes a four-bit sign field encoded to represent the polarity of the operand with the location of the sign field being different for the zoned and packed formats, automatic sign handling circuitry comprising:

• a first sign code detector for decoding the four bits at the zoned format sign field location in the first operand for producing a first polarity indicating signal;
• a second sign code detector for decoding the four bits at the packed format sign field location in the first operand for producing a second polarity indicating signal;
• a third sign code detector for decoding the four bits at the zoned format sign field location in the second operand for producing a third polarity indicating signal;
• a fourth sign code detector for decoding the four bits at the packed format sign field location in the second operand for producing a fourth polarity indicating signal;
• circuitry for enabling only the first and third sign code detectors when the operands are in a zoned format and for enabling only the second and fourth sign code detectors when the operands are in a packed format;
• a first exclusive OR circuit having one input coupled to the outputs of the first and second sign code detectors and a second input coupled to the outputs of the third and fourth sign code detectors;
• circuitry for receiving a requested operation signal indicating whether addition or subtraction is requested;
• and a second exclusive OR circuit having one input coupled to the output of the first exclusive OR circuit and a second input responsive to the requested operation signal for producing a control signal for controlling the arithmetic operation actually performed by the arithmetic circuitry.