BDC corrected adder

A BCD corrected adder having an addition mode and a subtraction mode, comprising:

• a. a serial adder circuit responsive to each bit of two bytes and to a formerly generated bit carry for generating a sum and a present bit carry;
• b. first means for generating a present byte carry whenever a present bit carry does not exist at the output of said adder during the addition of the most significant bit of a first byte and the most significant bit of a second byte, the result of which addition exceeds the decimal number ten in the addition mode;
• c. second means for generating a correction signal in response to the presence of one of said present carries during said addition in the addition mode, and for generating said correction signal in response to the absence of said present bit carry during the addition of the most significant bit of a minuend byte and the most significant bit of the 2's complement of a subtrahend byte in the subraction mode;
• and
• d. logic means connected to said serial adder and said first and second means responsive to the presence of said correction signal for generating simultaneously with the generation of said byte carry from said first means, each bit of a byte which is equal to the summation of said first byte, said second byte, and a byte equivalent to the decimal number six in the addition mode, and for generating simultaneously with the generation of said byte carry from said first means each bit of a byte which is equal to the summation of said minuend byte, the 2's complement of said subtrahend byte, and a byte equivalent to the decimal number ten in the subtraction mode.