US 3,999,080 A · Transistor coupled logic circuit

Abstract

A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.

Claims22

Dependent claims

A logic circuit comprising at least two first input transistors, a second multi-emitter transistor and a third output transistor, said first transistors being of complementary conductivity type to that of said second and third transistors, circuit means connecting first and second emitters of said second transistor respectively to the collector and the base of said third transistor for permitting said third transistor to conduct only in an unsaturated mode;

transistor load circuit means having a fourth transistor whose emitter is connected to the collector of said third transistor;
circuit means connecting the collector of the second transistor to said transistor load circuit means;
and circuit means connecting the emitters of said first transistors to the base of said second transistor such that when each said first transistor is turned off, said second and third transistors are turned on to provide a first logic signal level at the collector of said third transistor, and when any said first transistor is in a conductive state, said second and third transistors are turned off and said transistor load circuit means becomes conductive to provide a second logic signal level at the collector of said third transistor.

A logic circuit including at least two PNP input transistors having their emitters respectively connected to the input of an NPN emitter-follower stage, the output of said emitter-follower stage connected to the base of a multi-emitter NPN transistor, an NPN output transistor, circuit means connecting the first and second emitters of said multi-emitter NPN transistor respectively to the collector and the base of said output transistor for permitting said output transistor to conduct only in a non-saturated mode;

said multi-emitter transistor having a collector connected to the base input of an NPN Darlington pair having an emitter output connected to the collector of said output transistor, wherein said input transistors are in a conductive state, said multi-emitter transistor is conductive and drives said output transistor to a non-saturated conductive state resulting in a logic 0 signal at the collector of said output transistor;
and wherein when at least one of said input transistors is in a non-conductive state said multi-emitter transistor is non-conductive and said Darlington pair conducts to provide a logical 1 output signal at the collector of said output transistor.

A transistor coupled logic circuit comprising a plurality of first input transistors, a second multi-emitter transistor and a third output transistor, said first input transistor being of complementary conductivity type to that of said second and third transistors;

circuit means connecting first and second emitters of said second transistor respectively to the collector and base of said third transistor;
a Darlington pair transistor stage;
collector circuit means connecting the collector of said third transistor to said Darlington pair transistor;
conductive means connecting the collector of the second transistor to the base input of said Darlington pair stage;
non-inverting transistor circuit means connecting the emitter of each said first input transistor to the base of the second transistor such that when said first transistors are turned off, said second and third transistors are turned on to provide a first logic signal level at the collector of said third transistor, said first logic signal level being clamped at the V.sub.BE level of said third transistor and when said first transistor is in a conductive state, said second and third transistors are turned off and said Darlington pair transistor becomes conductive to provide a second logic signal level at the collector of said third transistor;
and n p-n diode junctions connected in series to the base input of said Darlington pair transistor stage for clamping said second logic signal level at a value equal to V.sub.BE volts.

3 more elements

A transistor coupled logic circuit comprising at least two first input transistors, a second transistor and a third output transistor, each first transistor being of complementary conductivity type to that of said second and third transistors;

first circuit means coupling the emitter of each first transistor to the base of the second transistor for switching said second transistor between conductive and non-conductive states in response to predetermined input signal conditions at the base of each input transistor;
circuit means coupling the emitter of the second transistor to the base of the third output transistor such that when the second transistor is in a conductive state, said third output transistor conducts to provide a first logic signal at the collector thereof;
said third output transistor having a collector circuit including transistor load means having an input cooperatively coupled with the collector of said second transistor such that switching of said second transistor to a conductive state biases the transistor load means to a non-conductive condition and switching of said second transistor to a non-conductive state biases the transistor load means to a conductive condition to provide a second logic signal level at the collector of said third transistor;
and p-n diode junction means cooperatively connected to the load transistor means to clamp said second logic signal level at a predetermined value.

1 more element

Dependencies are inferred from the claim text.

Transistor coupled logic circuit

Life of this patent

Transistor coupled logic circuit

Life of this patent

Abstract

Claims22