Apparatus and machine implementable method for the dynamic rearrangement of plural bit equal-length records
AssigneeInternational Business Machines Corporation
InventorsTien Chi Chen, Chin Tung
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AssigneeInternational Business Machines Corporation
InventorsTien Chi Chen, Chin Tung
Estimating the term…
An apparatus for performing efficient transposition exchange sorts among equal length records is described. The apparatus takes advantage of the flow steering property of linkable circulating storage loops to minimize the average access time by positioning information closer to the output port in a storage structure. The apparatus is formed from a linear array of equal size shift register loops each holding one record. The loops are switchably interconnected such that when two boundary switches are set in a first mode, the contents of each loop normally circulate wholly therewithin. Upon a common boundary switch being set in a second mode, the contents within a first loop flow into a second loop and vis-a-vis. By setting a common boundary switch to the second mode, the contents of a pair of adjacent loops are exchanged in the duration of one loop cycle time. Further exchanges can be started before a previous one is complete; this overlapping of operations can lead to an effective exchange rate of two exchanges per loop cycle. By repeating the exchange for consecutive pairs of loops, then the contents of any reference loop can be migrated to an output port D loops away in (D + 1)/2 loop cycle times.
In an apparatus for rearranging N identifiable 2m bit equal fixed length records `R.sub.i `, said apparatus including an externally controllable permutation network;
A method for rearranging in a predetermined manner N identifiable 2m bit equal fixed length records `R.sub.i ` stored in N equal length shift register loops `L.sub.j `, one record to each loop, each loop having a latency of 2m bit times, said loops being connected by N-1 selectively operable dual mode switches `S.sub.k ` to form a linked linear ladder structure, said loops and switches from end-to-end being lexically designated L.sub.0 to L.sub.N.sub.-1 and S.sub.0 to S.sub.N.sub.-1 ;
A method for rearranging in a predetermined manner N identifiable 2m bit equal fixed length records `R.sub.1 ` stored in N equal length shift register loops `L.sub.j `, one record to each loop, each loop having a latency of 2m bit times, said loops being connected by N.sub.-1 selectively operable dual mode switches `S.sub.k ` to form a linked linear ladder structure, said loops and switches from end-to-end being lexically designated L.sub.0 to L.sub.N.sub.-1 and S.sub.0 to S.sub.N.sub.-1 ;
A method for rearranging in a predetermined manner 2M identifiable 2m bit equal fixed length records stored in 2m equal shift register loops `L.sub.j `, one record for each loop, each loop having a loop latency of 2m bit times, said loops being connected by 2M-1 selectively operable dual mode switches `S.sub.k ` to form a linked linear structure, said loops and switches from end-to-end being lexically designated L.sub.0 to L.sub.2M.sub.-1 and S.sub.1 to S.sub.2M.sub.-1 ;
A method for rearranging in a predetermined manner N identifiable 2m bit equal fixed length records `R.sub.i `, the record format having front and back halves, the records being storable in corresponding ones of N equal length shift register loops `L.sub.j `, each loop having a latency of 2m bit times, said loops being connected by N-1 selectively operable dual mode switches `S.sub.k ` to form a linked linear ladder structure, said loops and switches from end-to-end being lexically designated L.sub.0 to L.sub.N.sub.-1 and S.sub.0 to S.sub.N.sub.-1, the switch S.sub.N.sub.-1 for a loop L.sub.N.sub.-1 or switches S.sub.i and S.sub.i.sub.+1 bounding any given loop L.sub.i other than L.sub.N.sub.-1, upon being set into a first mode, maintains the given loop as a circulation path;
An improved externally controllable permutation network for reordering N identifiable 2m bit equal fixed length records comprising:
A method for rearranging in a predetermined manner N identifiable 2m bit equal fixed length records `R.sub.i ` stored in N equal length shift register loops `L.sub.j `, one record to each loop, each loop having a latency of 2m bit times, said loops being connected by N-1 selectively operable dual mode switches `S.sub.k ` to form a linked linear ladder structure, said loops and switches from end-to-end being lexically designated L.sub.0 to L.sub.N.sub.-1 and S.sub.0 to S.sub.N.sub.-1 ;
Dependencies are inferred from the claim text.