US 3,993,993 AGranted

Digital-to-synchro converter

AssigneeRCA Corporation

InventorEarl Harris Griffin

Life of this patent

Estimating the term…

Abstract

A digital-to-synchro converter accepts digital distance data comprising either a binary coded decimal (BCD) signal or a train of pulses of any desired format. The converter comprises a digital-to-synchro converter whose output represents the distance data that controls a signal generator synchronized to a sinusoidal reference voltage. The signal generator output are pulses representing sample and hold control signals which are applied to a sample and hold circuit. The sine wave is sampled by the sample and hold circuit, and the output is a DC voltage that is proportional to the sine of the desirable synchro rotation angle. This voltage is applied to an analog multiplier for generating the controlling signals which are then amplified before being routed to provide distance measurements at the synchro receiver.

Claims4

Dependent claims

A digital-to-synchro converter including input means for receiving input data in the form of digital signals representing distance, said converter being suitable for driving a synchro receiver of the type having stator windings spatially separated in predetermined phase relation and a rotor rotatable an angular displacement proportional to the linear distance represented by said digital signals, the windings of said synchro receiver being adapted for excitation by sinusoidal voltages at a first frequency, comprising in combination:

a. a voltage source for providing a sinusoidal reference signal at said first frequency,
b. means responsive to said sinusoidal reference signal for generating a square wave reference signal at said first frequency,
c. means for coupling said sinusoidal reference signal to said rotor for energizing said rotor,
d. phase locked loop means responsive to said square wave signal for generating a first clock signal,
e. divider means responsive to said first clock signal for generating a second clock signal at a frequency that is a selected fraction of said first clock signal,
f. variable delay means responsive to said digital signals, to said square wave reference signal and to said second clock signal, for generating a variable delayed signal delayed, relative to said square wave reference signal, a phase angle proportional to the distance represented by said digital signals,
g. fixed delay means responsive to said variable delayed signal and to said first clock signal for generating a first delay signal having a phase angle summed from said variable delayed signal phase angle and a first fixed delay phase angle, and for providing a second delay signal having a phase angle summed from said variable delayed signal phase angle and a second fixed delay phase angle,
said first and second fixed delay phase angles being related to the phase separation of said stator windings such that in the absence of said variable delayed signal said rotor is oriented in a position corresponding to zero distance,
h. sampling means for sampling said sinusoidal reference signal in response to said first and second delay signals for generating a pair of D.C. signals each having a magnitude respectively representing a trigonometric function of the respective phase angles of said first and second delayed signals, and
i. analogue multiplying means for multiplying said pair of D.C. signals with said sinusoidal reference signal for generating a control signal for said synchro receiver stator windings to effect step-wise rotation of the rotor thereof an angular displacement corresponding to said distance represented by said digital signals, the magnitude of each of said steps being determined by said second clock signal.

7 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

a. a voltage source for providing a sinusoidal reference signal at said first frequency,
b. means responsive to said sinusoidal reference signal for generating a square wave reference signal at said first frequency,
c. means for coupling said sinusoidal reference signal to said rotor for energizing said rotor,
d. phase locked loop means responsive to said square wave signal for generating a first clock signal,
e. divider means responsive to said first clock signal for generating a second clock signal at a frequency that is a selected fraction of said first clock signal,
f. variable delay means responsive to said digital signals, to said square wave reference signal and to said second clock signal, for generating a variable delayed signal delayed, relative to said square wave reference signal, a phase angle proportional to the distance represented by said digital signals,
g. fixed delay means responsive to said variable delayed signal and to said first clock signal for generating a first delay signal having a phase angle summed from said variable delayed signal phase angle and a first fixed delay phase angle, and for providing a second delay signal having a phase angle summed from said variable delayed signal phase angle and a second fixed delay phase angle,
said first and second fixed delay phase angles being related to the phase separation of said stator windings such that in the absence of said variable delayed signal said rotor is oriented in a position corresponding to zero distance,
h. sampling means for sampling said sinusoidal reference signal in response to said first and second delay signals for generating a pair of D.C. signals each having a magnitude respectively representing a trigonometric function of the respective phase angles of said first and second delayed signals, and
i. analogue multiplying means for multiplying said pair of D.C. signals with said sinusoidal reference signal for generating a control signal for said synchro receiver stator windings to effect step-wise rotation of the rotor thereof an angular displacement corresponding to said distance represented by said digital signals, the magnitude of each of said steps being determined by said second clock signal.

7 more elements