Receiver equalizer apparatus

A discrete time signal filter having an adaptable filter characteristic for filtering discrete time input signals, said filter comprising:

• a first tapped delay means through which said discrete input signal passes after being provided at a first tapped delay means input, said first tapped delay means provided with a first tap output at which substantially said discrete input signal appears as a first tap output signal after a selected delay from when provided at said first tapped delay means input;
• a first multiplier means to receive said first tap output signal from said first tap output, said first multiplier means capable of multiplying said first tap output signal by a first multiplier signal to provide a first contribution signal, said first mutliplier means subject to being adjusted to alter values of said first multiplier signal;
• a summing means which provides as an output signal a summed contribution signal that represents a sum of signals presented to said summing means, said first contribution signal being presented to said summing means;
• a first adjusting means capable, when not prevented, of adjusting said first multiplier means to alter values of said first multiplier signal by first fixed increment changes therein, either to increase or to decrease values of said first multiplier signal, said first adjusting means initiating each such first fixed increment change in response to said first tap output signal in conjunction with an error signal derived from said summed contribution signal in conjunction with an estimated output signal which is also derived from said summed contribution signal, with series of said first fixed increment changes used to provide said adaptive filter characteristic;
• a first inhibitory means, said first inhibitory means capable of selectively preventing said first adjusting means from adjusting, in manner aforesaid, said first multiplier means in response to a first comparator means output signal;
• and
• a first comparator means which provides said first comparator means output signal depending on whether said first tap output signal exceeds a selected first threshold value.

A digital signal filter having adaptable filter characteristics for filtering digital input signals comprising sequentially presented discrete time input data samples formed as m-bit digital words, there being one said input data sample provided per sample period including a said input data sample provided in a first sample period, said filter comprising:

• a sample storage shift register means, capable of storing N digital words of m-bits, to receive said digital input signal and to store both said input data sample received in said first sample period and said input data samples received in (N-1) sample periods immediately preceding said first sample period, said sample storage shift register means being capable of presenting in an ordered sequence, ordered by time of receipt, each said stored input data sample at an output thereof within said first sample period to form a sample storage shift register output signal, and said sample storage shift register means being capable of recirculating said sample storage shift register output signal in said first sample period back through said sample storage shift register means while discarding in said first sample period that said stored input sample which was earliest received;
• a weighting storage shift register means capable of storing N words of (q+r) bits having an up/down counter means in a first storage position of said weighting storage shift register means, said up/down counter means to receive single bits representing weighting changes and being capable of using each said weighting change received to increment therein by increase or decrease, an existing count of said weighting changes previously recieved to form a weighting factor in form of a digital word of (q+r) bits, said weighting storage shift register means being capable of presenting in an ordered sequence each said weighting factor, corresponding through initial relative shift register storage position to each said stored input data sample, at an output thereof in said first sample period to form a weighting storage shift register output signal corresponding to said sample storage shift register output signal, and said weighting storage shift register means being capable of recirculating said weighting storage shift register output signal in said first sample period back through said first storage position and remainder of said weighting storage shift register means;
• a digital multiplier means to receive both said storage shift register output signal and said weighting storage shift register output signal, such digital multiplier means being capable of multiplying together each said stored input data sample in said sample storage shift register output signal with m most significant bits of each said corresponding weighting factor in said tap weighting storage shift register output signal in said first sample period to form sequentially, as digital words, N multiplication products in said first sample period, said digital multiplier means being capable of presenting said N multiplication products sequentially as formed at an output thereof in said first sample period to form a digital multiplier output signal;
• an accumulator means to receive said digital multiplier output signal, said accumulator means being capable of providing a total in said first sample period of said N multiplication products received in said first sample period in form of an accumulator output digital word of m bits, said accumulator means to present said accumulator output digital word at an output thereof to form a filter output signal;
• a level detector means to receive said filter output signal, said level detector means being capable of determining which allowed transmitted signal level each said accumulator output digital word is most nearly equal to in said first sample period said accumulator means capable of providing said determined allowed transmitted signal level in form of an estimated output digital word of m bits at an output thereof in said first sample period to thereby form an estimated output signal, said level detector means being capable of further determining a sign of that difference which results between said accumulator output digital word and corresonding said estimated output digital word and of providing a current error bit in said first sample period representing said sign as a sign bit error signal;
• a modulo-2 adder means to provide at an output thereoof in said first sample period single bits representing said weighting changes to form a weighting change output signal, each said weighting change being provided to said up/down counter as that said weighting factor corresponding thereto is recirculated through said first storage position, each said weighting factor corresponding to each said weighting change also corresponding to a preceding input data sample with which said weighting factor was multiplied in said digital multiplier means in a sample period preceding said first sample period in manner of multiplication occuring in said digital multiplier means in said first sample period as said above, each said weighting change being provided in response to a result of modulo-2 adding (i) a sign bit of each corresponding said preceding input data sample, all such sign bits received by said modulo-2 adder means obtained from said digital input signal to form a first adder input signal, to (ii) a preceding error bit, formed in said level detector means in said sample period preceding said first sample period in manner of forming said current error bit to form a delayed signal bit error signal received by said modulo-2 adder means;
• and
• a comparator means to receive a comparator means input signal obtained from said digital input signal, said comparator means being capable of determining whether magnitude portions of each said preceding input data sample exceeds a threshold value and further being capable of preventing said incrementing of said up/down counter means by each said weighting change corresponding to each said preceding input data sample having a magnitude portion which does not exceed said threshold.