Digital-to-analog decoder utilizing time interpolation and reversible accumulation
AssigneeBell Telephone Laboratories, Incorporated
InventorsJames Charles Candy, William Herbert Ninke, Bruce Allen Wooley
Life of this patent
Estimating the term…
Abstract
In each character time of a pulse code modulation signal stream, the most significant bit group of the PCM character is reversibly incremented and decremented a plurality of times. The incrementing and decrementing is carried out in a selectable sequence for each discrete pair of subintervals in the character time. The selectable sequences are determined by the value of the least significant bit group of the character whereby the average value, over the character time of an analog signal derived from the changing most significant bit group information in each subinterval, is equal to the value represented by the character.
Claims11
A decoder for producing a stepped analog signal from a companded pulse code modulation character having a plurality of magnitude bits, the signal having an average analog value over the character time which is substantially equal to the coded value of the character, said decoder comprising
- means for translating a first most significant group of said magnitude bits, representing in binary code the number of an amplitude segment in the coding system of said character, into an n:m code character representing in binary code the amplitude of a level at a boundary of said segment,
- a reversible shift register,
- means for coupling shift clock signals to said shift register,
- means for loading the n:m code character into said reversible shift register to overwrite all prior contents,
- means for deriving from said shift register an output analog signal having an amplitude corresponding by a predetermined algebraic rule to the analog information value represented by the contents of said shift register,
- means, responsive to a second less significant group of magnitude bits representing in binary code the number of an interval within said segment in said coding system, for producing a train of pulses having in said character time a number of pulses equal to said interval number, and
- means, jointly responsive to said shift clock signals and said train of pulses, for controlling the direction of operation of said shift register to have one shift in each direction in response to each pair of adjacent clock signals, said rule being selected so that said output analog signals during said clock signals in said character time have said average analog value.
A decoder for producing a stepped analog signal from a pulse code modulation character, which signal has an average analog value over the character time which is substantially equal to the coded value of the character, said decoder comprising
- means for reversibly accumulating digital information,
- means for presetting said accumulating means to a binary coded value corresponding to the value of analog information represented by a most significant bit portion of said character,
- means for actuating said accumulating means to increment or decrement said preset coded value one step at a time, in a three-step range in which said preset value is the intermediate step, in an ordered incrementing system, during each of plural periodically recurring time intervals between successive presettings of said accumulating means,
- means responsive to a least significant bit portion of said character, for controlling the pattern of incrementing and decrementing functions during said intervals, and
- means for deriving from said accumulating means an analog signal having an amplitude in each of said intervals corresponding to the value at that time of the binary coded contents of said accumulating means.
A digital-to-analog decoder for producing a stepped analog signal from each of a plurality of pulse code modulation words, and in which the average value of the output over a pulse code modulation work time is substantially equal to the value of the decoder input work at that time, and in which the bits of such input word are segregated into a first group of most significant bits and a second group of least significant bits, the least significant one of those bit groups being utilized to control the operation of a binary rate multiplier, and the decoder being CHARACTERIZED IN THAT,
- a code translator converts the most significant bit group of each pulse coded word into a shift companded code word,
- the translator output is loaded into a reversible shift register at the pulse code word rate, and
- logic circuits are provided for recurrently reversing the direction of operation of the shift register during each pulse code word time in accordance with the output of the binary rate multiplier and a clock signal occurring at one-half of the shift clock rate of the shift register, such logic circuits causing the register to shift either in a first or in a second direction at shifting times thereof if the binary rate multiplier output and the one-half clock rate signals are either in the same binary signal state or in different binary signal states, respectively.
Dependencies are inferred from the claim text.