Charge transfer memories
AssigneeRCA Corporation
InventorPaul Kessler Weimer
Life of this patent
Estimating the term…
Abstract
Charge transfer memories such as those of the bucket-brigade or of the charge-coupled device (CCD) type include, at each location, a store which is separate from the normal means for charge storage. Charge is transferred from the normal means of storage to the separate store at each location during a first period of time and may be sensed during later intervals of time to provide multiple "copies" of the stored information. In one form of such a memory especially suitable for the storage of digital data, each separate store includes an internal loop for refreshing the charge. In other forms of such memories, means are provided for reducing the effects of variation in threshold voltage from location-to-location of the transistors associated with the separate stores. These are especially suitable for analog storage.
Claims21
A charge transfer storage circuit comprising, in combination:
- a charge transfer stage which includes a node at which charge may be stored;
- a storage element;
- means operative during one time interval for transferring charge from said node to said storage element,
- charge conducting means;
- and
- means operative for during a following time interval for transferring charge between said charge conducting means and said node under control of the charge in said storage element, said means for transferring comprising a transistor having a conduction path and a control electrode for controlling the conductivity of said path, said path being connected between said charge conducting means and said node, and said storage element being connected to said control electrode.
A charge transfer storage circuit comprising, in combination:
- a plurality of charge transfer stages, each including a node at which charge may be stored;
- a like plurality of storage elements, one for each stage;
- and
- at each location, a circulation loop comprising:
- a. means for transferring the charge at said node at said location to said storage element for that location;
- b. means responsive to the charge at said storage element for inserting a refreshed charge at said node;
- c. means for erasing the charge stored at said storage element;
- and
- d. means for transferring said refreshed charge from said node to said storage element.
A charge transfer storage circuit comprising, in combination:
- a plurality of interconnected charge transfer stages;
- and
- a like plurality of recirculation loops for locally refreshing the stored charges, one coupled to each stage.
A charge transfer storage circuit comprising, in combination:
- a charge transfer stage which includes a node at which charge may be stored;
- first and second charge storage means;
- means for transferring the charge at said node to said first charge storage means;
- a second node;
- a source of charge carriers;
- a controllable charge conduction path connected at one end to said second node;
- means for supplying charge at a reference level to the other end of said conduction path while turning on said conduction path to thereby store a charge at a reference level at said second node;
- means for transferring the charge at said first charge storage means to said second charge storage means;
- means for turning on said conduction path during the transfer of charge from said first to said second storage means;
- and
- means including means responsive to the charge in said second storage means for transferring from said second to said first node through said conduction path an amount of charge complementary to that stored in said second storage means.
In a charge transfer circuit which includes a charge transfer stage having a first node at which charge may be stored and which includes also a second node at which a charge proportional to that at said first node may be stored to permit future copies to be made of charge proportional to that stored at the second node, in combination;
- means for transferring from said first node to said second node the charge stored at said first node;
- a third node;
- a conduction path connected at one end to said third node;
- means for applying charge through said conduction path to said third node for establishing charge at a reference level at said third node;
- and
- means under the control of the charge stored at said second node for removing from said third node through said conduction path to said first node an amount of charge proportional to that stored at said second node.
A charge transfer circuit comprising, in combination:
- a charge transfer register including at each stage at least first and second storage elements;
- a third charge transfer element associated with each stage;
- and
- means at each stage responsive to a control signal manifestation for transferring charge signal from the first storage element of that stage to the third charge transfer element associated with that stage, and for producing a copy of that charge signal and placing it in the second storage element of that stage.
A charge transfer circuit comprising, in combination:
- a charge transfer register including a plurality of stages;
- means for removing from each stage of the register a charge proportional to that stored at each stage;
- means responsive to a control signal manifestation and to the charge removed from each stage for producing a copy charge proportional thereto, said means including a common charge source and including also at each stage a conduction path, a storage node, and means for transferring charge in one direction from said source through said conduction path to said storage node;
- and
- means responsive to a control signal manifestation for transferring the copy charge produced at each stage in the opposite direction through said conduction path to said register stage.
Dependencies are inferred from the claim text.