Dual two-phase clock system
AssigneeGeneral Instrument Corporation
InventorJohn J. Wunner
Life of this patent
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Abstract
A new and improved clock system is described which is effective to substantially increase speed of operation of logic circuits without the need for additional power. That system includes the use of two sets of like phased clock signals, one of which is applied to the internal circuitry and the other of which controls the input and output stages of the circuit. By apportioning the capacitive load on the clock generator, the slower switching input and output circuitry is provided with faster switching clock signals exhibiting increased usable clock time while the faster switching internal circuitry is provided with less usable clock time. As a result, the available clock power is used to maximum efficiency and circuit speed is increased to the limit of the switching capabilities of the internal circuitry.
Claims24
In a semiconductor circuit comprising a plurality of switching means adapted to be actuated under the control of timed clock signals and when so actuated to transfer signals therethrough, at least one of said switching means having a relatively small capacitance and requiring more usable clock time for transferring signals than others of said switching means having a relatively large capacitance in the aggregate, the improvement comprising means for generating two sets of clock signals, each set comprising a plurality of substantially out-of-phase signals and the corresponding signals of each set respectively being substantially like-phased, and means operatively connecting one of said sets of clock signals to said at least one of said switch means and the other of said sets of clock signals to others of said switching means, whereby the capacitance encountered by the clock signal generating means in clocking said at least one switching means is less than the total capacitance of the others of said plurality of switching means thereby to provide the said at least one switching means with relatively more usable clock time for signal transfer than said plurality of switching means.
A clock generator circuit for generating first and second sets of clock signals from a clock input signal, each set comprising a plurality of substantially out-of-phase signals and the corresponding signal of each set respectively being substantially like-phased, said circuit comprising a plurality of first sub-circuits each having an input port and an output port and comprising at least two inverter stages, one of said first subcircuits receiving said clock input signal at its input port, the others of said first subcircuits having their input ports connected to the output of the first inverter stage of said one of said first subcircuits, and a plurality of second subcircuits each having an input port and an output port, the input ports of said second subcircuits being operatively connected to the outputs of the second inverter stages of said first subcircuits, respectively.
Dependencies are inferred from the claim text.