Expandable digital arithmetic logic register stack
AssigneeFairchild Camera and Instrument Corporation
InventorsCharles Erickson, Krishna Rallapalli, Peter W. J. Verhofstadt
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Abstract
An arithmetic logic register stack device is provided on a single semiconductor chip, which device comprises a building block for digital systems. The device of this invention is expandable, which enables performing operations with binary numbers greater than that with which a single device is capable of performing. Unique circuit design is provided for multiple use of connector pins to the semiconductor device, thereby allowing for an increase in the complexity of the circuits that can be integrated onto a single semiconductor chip or placed into a package with a given number of pins.
Claims16
A single chip large scale integration device, comprising:
- a. a memory disposed for storing data having an address input coupled to address input pins of said device, a data input, and a data output;
- b. an arithmetic logic unit having a first operand input coupled to data input pins of said device, a second operand input coupled to said data output of said memory, a result data output coupled to said data input of said memory, an instruction signal input coupled to instruction code input pins of said device, and a control signal output;
- c. an output register coupled between said result data output of said arithmetic logic unit and data output pins of said device;
- and,
- d. circuit means disposed for providing status output signals of said device on status output pins of said device, and having a first input coupled to said control signal output of said arithmetic logic unit, and a second input coupled to said instruction code input pins of said device.
An expandable digital arithmetic-logic register stack device, comprising:
- a. means for storing digital data having an address input, a data input, and a data output;
- b. means for performing arithmetic and logic operations having:
- i. a first operand input coupled to input terminals of said device,
- ii. a second operand input coupled to said data output of said means for storing,
- iii. a result data output coupled to said data input of said means for storing,
- iv. control signal input terminals disposed for receiving instruction codes indicative of arithmetic and logic operations to be performed;
- and,
- v. a control signal output disposed for providing signals indicative of the arithmetic and logic operations being performed;
- c. an output register coupled between said result data output of said means for performing and data output terminals of said device;
- and,
- d. circuit means disposed for providing status information of said device on status output terminals thereof, and having an input coupled to said control signal output of said means for performing.
A single chip digital circuit comprising:
- a. means for storing digital data having an address input coupled to address input pins of said chip, a data input and a data output,
- b. an arithmetic logic unit having a first operand input coupled to data input pins of said chip, a second operand input coupled to said data output of said means for storing, a result data output coupled to said data input of said means for storing, a control signal input and a control signal output;
- c. means for decoding instruction information supplied on instruction code input pins of said chip and having an output thereof coupled to the control signal input of said arithmetic logic unit;
- d. an output register coupled between said result data output of said arithmetic logic unit and data output pins of said chip;
- and,
- e. circuit means disposed for providing arithmetic carry information signals during arithmetic operations of said circuit and instruction information during logic operations of said circuit on status output pins of said chip in response to a first state of said circuit means, and for providing on said status signal output pins status information in response to a second state of said circuit means.
Dependencies are inferred from the claim text.