Method for generating pseudo-random bit sequence words and a device for carrying out the method
AssigneeU.S. Philips Corporation
InventorsLars Henning Zetterberg, Leif Ake Arvidsson
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Abstract
A method is obtained for generating pseudo-random bit sequence words which is characterized in that the bit contents of a given number of elements of the main register are used as an address for reading out from a memory of a corresponding superposition bit sequence of a length equal to the length of the main register and the bit sequence of a number of given elements of the main register are selected as a first word of the series.
Claims4
A method for generating pseudo-random bit-sequence words consisting of 0's and 1's by means of registers, and a series of such words each having a predetermined number of bits comprising the steps of
- supplying a starting bit pattern which is not entirely composed of 0's into a main register which comprise a predetermined number m + n of bistable elements, where m and n are integers;
- using the bit-contents of a predetermined number n of said elements of said main register as an address for reading out from a memory a corresponding superposition bit-sequence having a length equal to the length of said main register;
- selecting the bit-sequence of predetermined ones of said elements of said main register, corresponding to a word length of n bits as a first word of said series;
- modifying the bit sequence of the remaining m ones of said elements of said main register by transposing the bits in accordance with a predetermined reproducible transposition pattern;
- and
- simultaneously feeding back the result of said modifying step into the main register.
A device for generating pseudo-random bit sequence words, comprising a main register having m + n bistable elements, designated as m left and n right elements, where m and n are positive integrers;
- and inputs corresponding to said bistable elements;
- a secondary register having a predetermined number of bistable elements and adapted to collect the successively generated words of the pseudo-random bit sequence;
- an address register having n elements which are, respectively, connected in parallel to the n right elements of the main register, and an output;
- a memory having 2.sup.n positions each having the capacity of m + n bits for storing 2.sup.n superposition bit sequences, and having an address input connected to said output of said address register;
- a first addition register having the capacity of m + n bits for temporarily storing each of the superposition bit sequences which are supplied from said memory;
- and having an output;
- a second addition register for storing temporarily and shifting to the right by n steps the bit sequence of the m left elements of the main register, and having an output;
- and
- an addition device having 2 (m + n) inputs connected to corresponding outputs of said first and the second addition registers, and having m + n outputs connected to the respective inputs of the corresponding bistable elements of said main register, for addition modulo-2 of the contents of said first and second addition registers while feeding back simultaneously the result into said main register.
Dependencies are inferred from the claim text.