Memory diagnostic arrangement

For use with a memory system having first and second addressable memory modules;

• means for providing an address;
• means for providing a first enable signal when said first module is to be accessed and for providing a second enable signal when said second module is to be accessed;
• first access means controlled by said first enable signal for applying control signals including said address to leads extending to said first module to control the accessing of information stored therein, and for causing said leads extending to said first module to assume predetermined states in the absence of said first enable signal;
• and second access means controlled by said second enable signal for applying control signals including said address to leads extending to said second module to control the accessing of information stored therein;
• diagnostic apparatus comprising
• means connectable to said leads extending to said first module for detecting the states thereof and for providing an error indication if said leads are not in said predetermined states, and
• means jointly responsive to said error indication, to said second enable signal, and to the absence of said first enable signal for providing a malfunction signal thereby indicating a potential malfunction associated with said first access means and said first module while said second module is being accessed.

For use in an arrangement comprising

• an addressable memory including a plurality of volatile storage elements requiring periodic refreshing to maintain the viability of the information stored therein;
• control means for providing control information including an address identifying a group of said storage elements which are to refreshed and including one irrelevant address bit;
• first access means responsive to said control information for generating and applying a first set of signals including said address to said memory to refresh the information stored in predetermined ones of said storage elements in said group,
• second access means concurrently responsive to said control information for generating and applying a second set of signals including said address to said memory to refresh the information stored in the remaining ones of said storage elements in said group;
• first parity generating means for computing parity over said first set of signals;
• second parity generating means for computing parity over said second set of signals, and
• comparing said generating means for comparing said parities computed by said first and second parity generating means and for generating a mismatch signal when said parities do not match;
• a diagnostic apparatus comprising
• means for forcing said control means to cause said one irrelevant address bit to be in different states for said first and second access means to induct the generation of said mismatch signal, and
• means for storing said mismatch signal if generated by said comparing and generating means.

In an information system comprising a first and second memory, a diagnostic arrangement for checking the apparent operability of said first memory during periods of nonaccess comprising

• a source of control information for said first and second memories,
• means for providing a nonaccess indication specifying that said first memory is not being accessed,
• first access means responsive to said control information in the absence of said nonaccess indication for generating and applying a first set of signals to said first memory to control accessing of a predetermined portion of said first memory, and responsive to the presence of said nonaccess indication for causing said first set of signals to assume predetermined states,
• second access means responsive to said control information in the absence of said nonaccess indication for generating and applying a second set of signals to said second memory to control accessing of the remaining portion of said first memory, and responsive to the presence of said nonaccess indication for causing said second set of signals to assume said predetermined states,
• first parity means for computing parity over said first set of signals,
• second parity means for computing parity over said second set of signals,
• means for comparing said parities computed by said first and second parity means and for providing a mismatch indication for said first memory if said parities do not match,
• means for providing an access signal indicating that said second memory is being accessed, and
• first memory error signal generating means jointly responsive to said access signal, to said nonaccess indication and to said mismatch indication for generating an error signal for said first memory.

In an information system comprising first and second memories, a diagnostic arrangement for checking the apparent operability of said first memory during a period in which said first memory is not being accessed, which comprises,

• a source of control information for said first and second memories,
• means for providing a nonaccess indication indication that said first memory is not being accessed,
• access means responsive to said control information in the absence of said nonaccess indication for generating and then applying a set of signals to said first memory to control the accessing of information in said first memory, said access means also being responsive to said nonaccess indication for causing said set of signals to assume predetermined states,
• simulation means for indicating the expected predetermined states of said set of signals,
• means connected to said simulation means and to said access means for comparing said expected predetermined states with the actual states of said set of signals as applied to said first memory by said access means, and for providing a mismatch indication if said compared expected and actual states do not match, and
• error signal generator means jointly responsive to said mismatch indication and to said nonaccess indication for generating an error signal for said first memory.

In an information system, a diagnostic arrangement for checking the accessing of a memory including storage elements storing information which must be periodically refreshed to maintain the viability of such information, which comprises

• a source of control information comprising an access indication specifying whether or not said memory is to be accessed for either a read or write operation, and a refresh indication specifying whether or not said memory is to be accessed for a refresh operation,
• first access means, including buffer and logic means, responsive to said control information for generating and then applying a first set of signals to said memory to control the accessing of information in a predetermined portion of said memory if said control information specifies that said memory is to be accessed for a read, write, or refresh operation;
• and if said control information specifies that said memory is not to be accessed, said first access means for causing said first sset of signals to assume predetermined states and then for applying said predetermined first set of signals to said memory to inhibit the accessing of said predetermined memory portion,
• second access means, including buffer and logic means, responsive to said control information for generating and then applying a second set of signals to said memory to control the accessing of information in the remaining portion of said memory if said control information specifies that said memory is to be accessed for a read, write, or refresh operation;
• and if sadi control information specifies that said memory is not to be accessed, sadi second access means for causing said second set of signals to assume said predetermined states and then for applying said predetermined second set of signals to said memory to inhibit the accessing of said remaining memory portion,
• first parity generator means for computing parity over said first set of signals,
• second parity generator means for computing parity over said second set of signals,
• means for comparing said parities computed by said first and second parity generator means and for generating a mismatch signals when said parities do not match,
• means for providing an indication that another memory is to be accessed,
• a source of timing signals each indicating a timing point in the accessing of said memory or said other memory,
• means jointly responsive to specified ones of said timing signals and to said mismatch signal for generating a timed mismatch indication whenever a mismatch signal is present at one of said timing points indicated by one of said specified timing signals,
• first logic means jointly responsive to said timed mismatch indication and to said access indication for providing a first error signal if said access indication specifies that said memory is to be accessed for a read or write operation,
• second logic means jointly responstive to said timed mismatch indication and to said refresh indication for providing a second error signal if said refresh indication specifies that said memory is to be accessed for a refresh operation, and
• third logic means jointly responsive to said timed mismatch indication and to said indication that another memory is to be accessed for generating a third error signal.