Asynchronous multiplexer and demultiplexer combination

An asynchronous digital time division multiplex multiplexer and demultiplexer combination at one communication terminal to multiplex N asynchronous data transmit ports having a first mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the total rate of said first mixture of different bit rates and to demultiplex N asynchronous data receive ports having a second mixture of different bit reates from a received synchronous data stream having said data format and said given bit rate, where N is an integer greater than one, comprising:

• transmitting means coupled to a first propagation means to transmit said transmitted synchronous data stream on said first propagation means;
• N transmit circuits each coupled to a different one of said N transmit ports and in common to said transmitting means;
• receiving means coupled to a second propagation means to receive said received synchronous data stream from said second propagation means;
• N receive circuits coupled in common to said receiving means and each of said N receive circuits coupled to a different one of said N receive ports;
• first means coupled to said transmitting means to generate a first timing code identifying transmit time slots of said transmitted data stream;
• second means coupled to said receiving means responsive to said received data stream to generate a second timing code identifying receive time slots of said received data stream;
• and
• third means coupled to said first and second means and each of said N transmit and receive circuits, said third means responding sequentially to said first and second timing codes to produce transmit and receive port timing signals to control distribution of bits of each of said transmit ports with equal spacing throughout said transmit time slots and to control extraction of bits of each of said receive ports from said received data stream, said bits of each of said receive ports being distributed with equal spacing throughout said receive time slots, said distribution of said bits of each of said transmit and receive ports throughout said transmit and receive time slots being in agreement with its associated bit rate.