Planarization of integrated circuit surfaces through selective photoresist masking

A method for forming a dielectrically isolated integrated semiconductor circuit comprising

• forming in a semiconductor substrate a pattern of trenches extending from a surface of said substrate, said trench pattern laterally enclosing respectively a plurality of pockets of said semiconductor substrate,
• forming over said semiconductor substrate a layer of electrically insulative material whereby said layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas,
• forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated,
• flowing said photoresist pattern by treating said photoresist with a photoresist solvent to laterally expand the photoresist to cover and thereby mask said depressed areas, and
• etching to lower said undepressed areas of said insulative layer.

A method for forming a dielectrically isolated integrated semiconductor circuit comprising

• masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate.
• etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings,
• depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer, and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants,
• depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants,
• forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated,
• flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas,
• etching to lower said undepressed areas of said third layer and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed areas,
• etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and
• removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.

A method for forming a dielectrically isolated integrated semiconductor circuit comprising

• masking a semiconductor substrate surface with a first layer of electrically insulative material having a pattern of openings corresponding to trenches to be etched in the substrate,
• etching with an etchant which preferentially etches the semiconductor substrate material to form a pattern of trenches in said substrate extending from said surface, said etching being conducted for a time sufficient so that said trenches undercut said insulative layer adjacent said openings,
• depositing a second layer of electrically insulative material over said first layer and under the undercut portions of said first insulative layer and over the substrate exposed in said trenches, said first insulative material being more etchable than said second insulative material in selected etchants,
• depositing over said second insulative layer, a third layer of electrically insulative material whereby said third layer has a pattern of depressed areas corresponding to and filling said trench pattern and a complementary pattern of undepressed areas, said material of said third layer having a different etchability than said second insulative material in selected etchants,
• forming in said depressed areas a photoresist pattern in registration with said depressed area pattern, said photoresist pattern having narrower lateral dimensions than said depressed area pattern whereby registration is facilitated,
• flowing said photoresist pattern to laterally expand the photoresist to cover and thereby mask said depressed areas,
• etching to lower said undepressed areas of said third layer to the level of said depressed areas and to remove said undepressed areas of said third layer to expose the portions of the second insulative layer underlying said undepressed area,
• etching with an etchant which preferentially etches the material of the second layer to remove the exposed portions of said second layer, thereby exposing the underlying portions of the first layer, and
• removing selected portions of said exposed first layer from said substrate surface adjacent said trenches with an etchant which preferentially etches said first layer, said second layer under the undercut portions of said first layer protecting the substrate adjacent said trenches from lateral exposure during the etching.