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US 3,975,221 AGranted
Low capacitance V groove MOS NOR gate and method of manufacture
AssigneeAmerican Micro-Systems, Inc.
InventorThurman J. Rodgers
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Abstract
An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.
Claims13
A method of making a field effect transister device, comprising the steps of:
- providing a semiconductor crystal source substrate having donor and acceptor dopants in which the acceptor concentration is less than the donor dopant concentration;
- forming a drift region over the source substrate having a dopant concentration less than the acceptor dopant concentration of the source substrate;
- out diffusing acceptor dopant from the source substrate into the drift region to form a p-type base means;
- forming n-type drain means in the drift region;
- etching at least one V groove into the source substrate exposing portions of the base means and drift region;
- providing insulative material over the exposed portions to form a gate oxide;
- providing conductive material over the insulation material to form a gate electrode;
- and
- providing lead means in electrical communication with the base means and drain means.
6 more elements
Dependencies are inferred from the claim text.