Dynamic random access memory misfet integrated circuit

The random access memory which comprises a monolithic semiconductor chip having formed thereon:

• a matrix of storage cells arrayed in rows and columns, the storage cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and the data being transferred to and from each cell in each column by the corresponding column bus;
• a sense amp for each column bus for detecting the logic state of an enabled cell connected to the respective column bus as the cell is enabled and holding the detected logic state;
• row address means for enabling a row of storage cells designated by row address data;
• a row address strobe input for inputting a row address strobe signal to the chip;
• row address clock and control means responsive to a row address strobe signal on the row address strobe input for automatically causing an addressed row of storage cells to be enabled and the data in the storage cells of the row to be detected by the respective sense amp and held;
• a data bus;
• column address means responsive to a column address strobe signal input to the chip after the row address strobe signal for enabling an addressed sense amp to transfer data between the data bus and the enabled sense amp;
• and
• data transfer means for transferring data between the data bus and circuitry external to the chip.

The circuit for producing a clock signal above a drain supply voltage between first and second successive clock edges and substantially at a source supply voltage after the second clock edge until a precharge signal which occurs some period after the second clock edge and terminates before the next first clock edge which comprises:

• a precharge node,
• an output node,
• a capacitor coupling the precharge node and the output node,
• a first transistor connecting the precharge node to the drain supply voltage,
• a second transistor connecting the precharge node to the source supply voltage,
• a third transistor connecting the output node to the drain supply voltage, and
• a fourth transistor connecting the output node to the source supply voltage,
• the second and third transistors being turned on by the precharge signal, the first transistor being turned on by the first clock edge and the fourth transistor being turned off by the second clock edge.

In a random access memory formed on a monolithic semiconductor chip and having a plurality of memory cells each having a storage capacitor connected to a column bus when a transistor is turned on by an enabling signal, the method of detecting the logic level stored on the capacitor of an enabled cell which comprises:

• precharging the column bus to precharge voltage level,
• sampling the precharge voltage level on the column bus and storing the sampled voltage on a reference node,
• then enabling a selected storage cell by turning the transistor of the selected cell on,
• detecting a predetermined change in the column bus from the sampled voltage stored on the reference voltage, and
• changing the voltage level on the column bus in the event a predetermined change in the voltage level is detected, to a voltage level corresponding to the voltage level of the capacitor of the enable cell before the cell was enabled.

In a random access memory which comprises a monolithic semiconductor chip, the combination of:

• a matrix of storage cells arrayed in rows and columns, the storage cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and data being transferred to and from each cell in each column by the corresponding column bus;
• sense amp means for each column bus for discriminating between at least two voltage levels representative of logic states and holding the detected logic state;
• a plurality of binary row address inputs to the chip sufficient in number to binarily define the number of rows or columns, whichever is greater;
• a row address strobe input for inputting a row address strobe to the chip;
• row address decode means responsive to a row address strobe input to the chip for decoding row address data and holding the addressed row of memory cells enabled until termination of the row address cycle;
• a column address strobe input for inputting a column address strobe signal to the chip;
• column address latch means for storing column address data applied to said address inputs;
• and
• column address decoder means responsive to a column address strobe signal for enabling the transfer of data from the sense amp means for the column identified by the column address.

In a random access memory which comprises a monolithic semiconductor chip, the combination of:

• a matrix of storage cells arrayed in rows and columns;
• a plurality of address inputs limited in number to that required to define the greater of the number of rows or columns for inputting a corresponding number of address signals to the chip;
• strobe input means for inputting time spaced row address strobe and column address strobe signal to the chip;
• row address means responsive to a row address strobe input through the strobe input means for holding a row of storage cells defined by the address signals then on the address inputs enabled for processing of data therein;
• and
• column address means responsive to a column address strobe input through the strobe input means for holding the storage cells defined by the address signals then on the address inputs enabled for processing of data therein.

The method of addressing a selected memory cell of a matrix of memory cells arrayed in rows and columns on a monolithic semiconductor chip disposed in a multiple pin package which comprises:

• applying one binary input of a set of binary inputs which identify the row of selected memory cell to each of a set of address pins of the package;
• applying one address strobe signal to a pin of the package to cause the row address information on the set of address pins to be input and stored in the circuit;
• then
• applying each binary input of a set of binary inputs which identify the column of the selected memory to one of the same set of address pins of the package;
• and
• applying another address strobe signal to a pin of the package to cause to column address information on the set of address pins to be input to the circuit.

In a memory formed on a monolithic semiconductor chip of a field effect transistor and having a plurality of logic inputs to which logic input signals are normally applied in sequence in the operation of the memory, the input circuit comprising an inverter stage including:

• an output node for the inverter stage;
• a load impedance circuit including an impedance device and a first transistor connecting the output node to a drain voltage supply node so as to block any current through the impedance circuit when turned off;
• and
• an input circuit including at least a second transistor connecting the output node to a source supply voltage node, the gate of the second transistor being a logic input to the chip;
• the first transistor being turned on in response to a logic input signal normally applied to another logic input to the chip before a logic signal would normally be applied to the gate of the second transistor whereby the inverter stage will be turned off and not dissipate energy in the absence of the earlier logic signal.

In a random access memory formed on a monolithic semiconductor chip having a matrix of memory cells and logic means for addressing a selected memory cell of the matrix, the combination of

• strobe input means for inputting an externally generated strobe signal to the chip;
• first means for applying externally generated alternative logic levels to the chip for indicating that the chip is selected or not selected;
• second means for applying externally generated alternative logic levels to the chip for indicating a read cycle or a write cycle;
• and
• logic means responsive to an externally generated strobe signal applied to the strobe input means including data output latch means for:
• a. in the presense of a chip not selected logic level on the first means causing the data output to be an open circuit until responding to another strobe input signal,
• b. in the presence of a chip selected logic level on the first means and a read cycle logic level on the second means producing a logic output representative of the logic level stored in an addressed memory cell until responding to another strobe input signal, and
• c. in the presence of a chip selected logic level and a write logic level automatically storing data in an addressed memory cell and a predetermined state at the data output until responding to another strobe input signal.

In a random address memory formed on a monolithic chip and having a matrix of memory cells arrayed in rows and columns, a set of address inputs sufficient in number to logically define only the number of rows or columns, whichever is greater, strobe input means for sequentially inputting a row strobe signal and a column strobe signal to the chip, data means for inputting and outputting binary data from the chip, and read/write control input means for inputting a signal to the chip having a read logic strobe for a read common and write logic strobe for a write command, the method comprising:

• applying a set row address signals representing a row of memory cells in the matrix to the address inputs to the chip;
• gating the row address signals into the chip in response to a row strobe signal and then holding the row of memory cells identified by the row address signals enabled;
• applying a set of column address signals representing a column of memory cells in the matrix to the same address inputs to the chip;
• and
• gating the column address signals into the chip in response to a column strobe signal to enable the processing of data in the memory cell of the addressed row and the addressed column.