Protective circuit for field effect transistor amplifier

A field effect transistor amplifier comprising;

• a voltage source for supplying an operating voltage;
• first and second depletion-type field effect transistors each having gate, source and drain electrodes;
• means for applying said operating voltage across said drain and source electrodes of each of said first and second transistors through a load;
• input circuit means for applying an input signal to be amplified to said gate electrode of each of the field effect transistors so as to drive said first and second field effect transistors with a push-pull relationship therebetween;
• biasing circuit means for applying first and second predetermined DC gate bias voltages between the gate and source electrodes of said first and second field effect transistors, respectively;
• protective circuit means for preventing damage to said field effect transistor by an excessive input signal including first and second source resistors connected in series with the source electrodes of said first and second field effect transistors, respectively, first constant voltage means connected between the gate electrode of said first field effect transistor and the side of said first source resistor remote from the respective source electrode, and second constant voltage means connected between the gate electrode of said second field effect transistor and the side of said second source resistor remote from the respective source electrode, the resistance values of said first and second source resistors and the voltage values of said first and second constant voltage means being selected so that the maximum drain source current of each of said first and second field effect transistors, when operated with an input signal applied to its gate electrode, does not exceed the maximum drain-source current of the respective field effect transistor in the absence of any gate-source voltage applied thereto;
• shunting means operative to shunt said input signal directly to said load while said first and second DC gate bias voltages continue to be applied to said first and second field effect transistors;
• and detecting means for detecting an overload condition of each of said first and second field effect transistors including, for each of said first and second field effect transistors, a capacitor, a first rectifying circuit means having a diode and a resistor connected between the respective source resistor and said capacitor for applying to the latter a DC voltage of one polarity which is proportional to the voltage across said respective source resistor, a second rectifying circuit means having a diode and a resistor connected between said capacitor and said load for applying to said capacitor a DC voltage of the opposite polarity which is proportional to the voltage across said load so that the DC voltage across said capacitor is proportional to the impedance of said load, and means responsive to said DC voltage across the capacitor for operating said shunting means when said DC voltage across the capacitor is indicative of a predetermined low value of the load impedance.