Transistor bridge inverter motor drive having reduced harmonics

A harmonic-reduced, variable frequency and variable voltage power supply for a three phase a.c. motor comprising, in combination, a three phase bridge inverter having three phase legs each of which comprises first and second transistors connected in series across a d.c. power source and first and second feedback rectifiers connected in inverse parallel relation with said first and second transistors respectively, oscillator means for generating a succession of clock pulses whose frequency is a function of an analog speed signal, resettable volt/hertz integrator means for deriving a train of ramp pulses which are synchronized to said clock pulses and whose instantaneous magnitude varies as a function of the integral of the output voltage of said bridge inverter with respect to time, first and second comparators for deriving first (HVT) and second (LVT) control pulses when the voltage of each said ramp pulse becomes equal respectively to first and second reference voltages of different magnitude, means for disabling said integrator means at said first control pulse and for holding it disabled until the succeeding clock pulse, three phase generator means for deriving three phase reference waves (A, B, C) displaced 120.degree. whose edges are synchronized to said clock pulses and each of which has a period equal to the time required to generate a predetermined number of said clock pulses and has positive and negative half cycles, interval generator (IG) means for deriving three trains of step controlling signals (H1, H2, H3) each of which corresponds to one of said phase reference waves and which step controlling signals span respective zero crossings of said corresponding phase reference wave, volt-second switch means for deriving three trains of duty cycle regulating pulses (VT1, VT2, VT3) each of which is associated with one phase of said inverter bridge and which duty cycle regulating pulses have leading edges at said first control pulse HVT when the corresponding step controlling signal is absent and at said second control pulse (LVT) when the corresponding step controlling signal is present and whose trailing edges are at the succeeding clock pulse, and modulation means for generating three trains of transistor switching pulses (1a, 1b, 1c) each of which regulates the switching of said first transistor in one phase of said inverter bridge and which follows the complement (e.g., VT1) of said train of duty cycle regulating pulses during the positive half cycle (e.g., A) of the corresponding phase reference wave and follows said train (e.g., VT1) of duty cycle regulating pulses during the negative half cycle (e.g., A) of the corresponding phase reference wave.

A harmonic-reduced variable frequency and variable voltage power supply for a three phase a.c. motor (M) comprising a three phase bridge inverter bridge (INV) having three phase legs each of which comprises first (e.g., 1A) and second (e.g., 1B) transistors connected in series across a d.c. power source (BR) and first (1AD) and second (1BD) feedback rectifiers connected in inverse parallel relation with said first and second transistors respectively, oscillator means (VCO) for generating a succession of clock pulses (f1) whose frequency is a function of an analog speed signal, resettable volt/hertz integrator means (RI) for deriving a train of ramp pulses (v.sub.c14) which are synchronized to said clock pulses and whose instantaneous magnitude varies as a function of the integral of the output voltage of said bridge inverter with respect to time, first (LC1) and second (LC2) comparators for deriving first (HVT) and second (LVT) control pulses when the voltage of each said ramp pulse becomes equal respectively to first and second reference voltages, means (Q13) for disabling said integrator means at said first control pulse and for holding it disabled until the succeeding clock pulse, a frequency divider (DIV) for generating trains of first (f1'/6) and second (f1"/6) timing pulses each of whose frequency is equal to the quotient of the frequency of said clock pulses divided by an integer and which are displaced 180.degree. in phase, three phase generator means (GEN) receiving said train of first timing pulses (f1'/6) as an input for deriving three phase reference waves (A, B, C) displaced 120.degree. whose edges are synchronized to said clock pulses and each of which has a 360.degree. period equal to the time required to generate a predetermined number of said clock pulses and having positive and negative half cycles, interval generator means (IG) receiving said train of second timing pulses (f1"/6) and said three phase reference waves (A, B, C) as inputs for deriving three trains of step controlling signals (H1, H2, H3) each of which corresponds to one of said phase reference waves (A, B, C) and spans respective zero crossings of said corresponding phase reference wave, volt-second switch means (VSS) for deriving three trains of duty cycle regulating pulses (VT1, VT2, VT3) each of which is associated with one phase of said inverter bridge and which duty cycle regulating pulses have leading edges respectively at said first control pulse (HVT) when the corresponding step controlling signal (e.g., H1) is absent and at said second control pulse (LVT) when the corresponding step controlling signal is present and whose trailing edges are at the succeeding clock pulse, and modulation means (ML) for generating three trains of transistor switching pulses (1a, 1b, 1c) each of which regulates the switching of said first transistor (e.g., 1A) in one phase (e.g., .phi..sub.1) of said inverter bridge and which follows the complement (e.g., VT1) of said train of duty cycle regulating pulses during the positive half cycle (e.g., A) of the corresponding phase reference wave and follows said train of duty cycle regulating pulses (VT1) during the negative half cycle (A) of the corresponding phase reference wave.

Chopping pulse generating means for an n-phase bridge inverter having first and second series-connected transistors in each phase leg adapted to be connected across a d.c. source, comprising, in combination,

• oscillator means for generating a succession of clock pulses (f1) whose frequency is a function of an analog speed signal,
• resettable volt/hertz integrator means (RI) for deriving ramp pulses (v.sub.c14) which are synchronized to said clock pulses and whose instantaneous magnitude varies as a function of the integral of the output voltage from said inverter with respect to time,
• first (LC1) and second (LC2) comparators for deriving first (HVT) and second (LVT) control pulses when said ramp pulses become equal respectively to first and second reference voltages of different magnitude,
• n-phase generator means (GEN) for deriving n-phase reference waves (A, . . . N) displaced 360/n degrees apart having edges synchronized to said clock pulses (f1) and each of which is associated with one phase leg of said inverter bridge and has a 360.degree. period which includes a predetermined number of said clock pulses and has positive and negative half cycles,
• interval generator means (IG) for deriving n trains of step controlling signals (H1, . . . Hn) each of which corresponds to one of said reference waves (A, . . . N) and spans respective zero crossings thereof,
• volt-second switch means (VSS) for deriving n trains of duty cycle regulating pulses (VT1, . . . VTn) each of which corresponds to one of said reference waves (A, . . . N) and which pulses have leading edges at said first control pulse (HVT) and at said second control pulse (LVT) respectively when the corresponding step controlling signal (e.g., H1) is absent and is present, the trailing edges of said duty cycle regulating pulses being at the succeeding clock pulses, and
• modulation logic means for deriving n trains of harmonic-reduced transistor switching pulses (1a . . . na) each of which corresponds to one of said reference waves and regulates said first transistor (e.g., 1A) in the associated inverter phase leg (e.g., .phi..sub.1) and follows the complement (e.g., VT1) of said train of duty cycle regulating pulses during the positive half cycle of the corresponding reference wave (e.g., A) and follows said train (e.g., VT1) of duty cycle regulating pulses during the negative half cycle of said corresponding reference wave, said modulation logic means also deriving the complements (1b, . . . nb) of said trains of transistor switching pulses which respectively control said second transistors in the associated inverter phase legs.