Fixed point to floating point conversion in an electronic computer

In a digital electronic computer comprising:

• a memory including a first and a second register, the first register receptive of a number to be converted from fixed to floating point notation, the second register receptive of a significant zero digit associated with a decimal point;
• shifting means selectively operable too shift the contents of either of said registers;
• aligning means operable to control said shifting means to first shift the content of said second register until the decimal point stored therein is aligned with the decimal point stored in said first register;
• indicating means for indicating whether the number stored in said first register is greater or less than one;
• and control means responsive to said indicating means to control said shifting means to next shift the contents of one of said registers when said number is greater than one and alternatively to shift the contents of the other of said registers when said number is less than one, said control means including means for detecting the highest significant digit of the digits of said first register to stop said shifting means when the decimal point of said second register is aligned with the location of the next higher order with respect to the highest significant digit of said first register, and counting means responsive to said shifting means to effect said second register to be incremented or decremented by one in dependence upon the direction for each shifting, whereby the first register contains the mantissa and the second register contains the exponent of the floating point notation.