Calculating unit for serial multiplication including a shift register and change-over switching controlling the transmission of the multiplicand bits to form the product

A calculating unit for the serial multiplication of a binary multiplicand and a binary multiplier, comprising

• a calculating unit input for receiving the multiplicand in serial fashion, and a calculating unit output for supplying the product of the multiplier and multiplicand,
• a sign register for storing a sign digit signal in accordance with the sign of the multiplicand,
• a shift register having its output connected to the calculating unit output and having a series of storage cells into which the multiplicand is fed in response to calculating pulses of a calculating pulse train during a multiplication cycle of N calculating pulses,
• said shift register having an adder interposed in the series of storage cells and positioned in the series in accordance with a binary one multiplier digit of the multiplier to be represented thereby,
• a plurality of change-over switches each representing a respective binary one multiplier digit of the multiplier, and having first switch inputs connected in parallel to the calculating unit input, having second switch inputs connected in parallel to the sign register and having respective switch outputs connected with said shift register at positions thereof in accordance with the digit value of the binary one multiplier digit represented thereby, and operable in one switching condition to connect the calculating unit input with the respective switch outputs for supplying digit signals in accordance with the successive digits of the multiplicand to said shift register at positions thereof in accordance with the digit value of the binary one multiplier digit represented thereby, and operable in another switching condition to connect the sign register with the respective switch outputs for supplying digit signals in accordance with the sign digit signal stored by said sign register to the respective positions of the shift register,
• said change-over switches being responsive to respective switch control pulse trains during a multiplication cycle to connect the sign register with the kth switch output during the first k calculating pulses of the calculating pulse train where the respective switches represent a binary one multiplier digit of digit value 2.sup..sup.-k, and to connect the calculating unit input to the kth switch output during the remaining N minus k calculating pulses of the calculating pulse train, thereby to supply to the respective switch outputs digit signals in accordance with the stored sign digit signal during the first k calculating pulses of the calculating pulse train and to supply to the respective switch outputs digit signals from the calculating unit input during the remaining N minus k calculating pulses of the calculating pulse train.

A calculating unit for the serial multiplication of a binary multiplicand and a binary multiplier, comprising

• a calculating unit input for receiving successive digit signals representing successive digits of a binary multiplicand and a sign digit signal representing the sign of the multiplicand,
• a calculating unit output for supplying the successive digit signals representing the product of the multiplicand and a binary multiplier,
• a shift register connected with the calculating unit input and having a series of storage cells into which the successive digit signals are fed in serial fashion, and responsive to successive calculating pulses of a calculating pulse train to shift the successive digit signals through said series of storage cells during a multiplication cycle,
• a sign register to which the digit signal representing the sign digit of the multiplicand is supplied,
• an adder operatively connected with said shift register and responsive to the successive calculating pulses of the calculating pulse train to additively combine respective digit signals, and
• a series of individually operable change-over switches each representing a respective binary one multiplier digit of the multiplier, and operatively connected with said shift register, said adder and said sign register for controlling the processing of successive digit signals during the transmission thereof between said calculating unit input and said calculating unit output to effect the multiplication of said multiplicand and said multiplier, said switches each being operatively associated with a respective one of said storage cells of said series of storage cells in accordance with the digit value of the binary one multiplier digit represented thereby and each switch being controlled by a respective switch control pulse train which initiates a changeover in each multiplication cycle in accordance with the digit value of the binary one multiplier digit represented by the switch.