Current mode binary/BCD arithmetic array

A current mode arithmetic logic array for operating on pure binary and on binary coded decimal data comprising:

• a first array portion for receiving a carry input, a binary operation code, and first and second binary signal inputs and producing half-sum of said inputs and carry generate output signals in response to said binary operation code,
• a second array portion receiving said carry input, said half-sums and said carry generate signals and producing carry signals for each binary level of said first and second signals other than the least significant binary level,
• a third array portion responsive to said half-sum signals from said first portion, said carry signals from said second portion, and said operation code and producing a binary output resultant of the operation defined by said operation code on said first and second binary signals,
• a fourth array portion responsive to a Decimal Add (DA) signal for adding a count of six to one of said inputs prior to reception thereof by said first array portion, and
• a fifth array portion responsive to either a Decimal Add or a Decimal Subtract (DA + DS) signal for subtracting a count of six from the output from said third array portion if a carry output (C16) from said third array is not present,
• all of said array portions comprising soft saturating current mode logic series gates including a lower level gate and an upper level gate having an output voltage range limited to approximately 0.5 volt.