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US 3,955,269 AGranted
Fabricating high performance integrated bipolar and complementary field effect transistors
AssigneeInternational Business Machines Corporation
InventorsIngrid Emese Magdo, Steven Magdo
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Abstract
A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV.sub.ceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.
Claims23
A method for fabricating dielectrically isolated bipolar and field effect transistors comprising:
- introducing into a first region of a monocrystalline semiconductor substrate of a first conductivity type an impurity of the opposite conductivity type to form the subcollector region of said bipolar transistor;
- introducing impurities of said first conductivity type into second and third regions of said substrate, said second region surrounding said first region, the diffusion rate of the impurity in said first region being slower than the diffusion rate of the impurity in said third region;
- forming a first monocrystalline layer of said second conductivity type over said substrate, said impurities outdiffusing therein at their respective diffusion rates;
- introducing an added quantity of impurity into said second region;
- depositing a dielectric layer over said first monocrystalline layer;
- forming openings in said dielectric layer over said first region, said third region, and at another location over said first monocrystalline layer;
- epitaxially depositing a second layer of silicon over said dielectric layer and in said openings, thereby forming monocrystalline regions over the first monocrystalline layer exposed by said openings and polycrystalline regions over the insulating layer;
- the impurities in said third region outdiffusing into the monocrystalline region thereover, to form a channel region of a field effect transistor;
- the impurities in said first region outdiffusing sufficiently slowly so as not to come in contact with the monocrystalline region disposed thereover;
- dielectrically isolating said monocrystalline regions of said second epitaxial layer from one another;
- and
- selectively forming emitter and base regions of a bipolar transistor in said monocrystalline region disposed over said subcollector region, source and drain regions of a second conductivity type in the monocrystalline region disposed over said third region to form a field effect transistor of a second channel type, and source and drain regions of first conductivity type in the monocrystalline region disposed over said other location to form a field effect transistor at a first channel type.
9 more elements
A method for fabricating dielectrically isolated bipolar and field effect transistors comprising:
- introducing into a first region of a monocrystalline semiconductor substrate of a first conductivity type an impurity of the opposite conductivity type having a surface concentration between 6 .times. 10.sup.19 to 2 .times. 10.sup.20 atoms per cm.sup.3 to form the subcollector region of said bipolar transistor;
- introducing impurities of said first conductivity type having a surface concentration of at least 10.sup.20 atoms per cm.sup.3 into second and third regions of said substrate, said second region surrounding said first region, the diffusion rate of the impurity in said first region being slower than the diffusion rate of the impurity in said third region;
- forming a first monocrystalline layer of said second conductivity type having a doping level of 10.sup.16 atoms per cm.sup.3 or less over said substrate, said impurities outdiffusing therein at their respective diffusion rates;
- introducing an added quantity of impurity into said second region sufficient to increase its doping level at the upper surface of said first monocrystalline layer to at least 5 .times. 10.sup.17 atoms per cm.sup.3 ;
- depositing a dielectric layer over said first monocrystalline layer;
- forming openings in said dielectric layer over said first region, said third region, and at another location over said first monocrystalline layer;
- epitaxially depositing a second layer of silicon having a thickness between 0.5 and 1.0 microns over said dielectric layer and in said openings, thereby forming monocrystalline regions over the first monocrystalline layer exposed by said openings and polycrystalline regions over the insulating layer;
- impurities in said third region outdiffusing into the monocrystalline region thereover, to form a channel region of a field effect transistor;
- the impurities in said first region outdiffusing sufficiently slowly so as not to come in contact with the monocrystalline region disposed thereover;
- dielectrically isolating said monocrystalline regions of said second epitaxial layer from one another;
- and
- selectively forming emitter and base regions of a bipolar transistor in said monocrystalline region disposed over said subcollector region, source and drain regions of a second conductivity type in the monocrystalline region disposed over said third region to form a field effect transistor of a second channel type, and source and drain regions of first conductivity type in the monocrystalline region disposed over said other location to form a field effect transistor at a first channel type;
- the distance between said base region and said first region being around 1.2 microns.
10 more elements
Dependencies are inferred from the claim text.