Charge transfer device signal processing system

A programmable matched filter comprising:

• a. charge transfer delay means having a plurality of stages each defining at least one signal storage node;
• b. positive and negative signal summation buses;
• c. detector means for each stage of said delay line, each detector means including:
• i. an insulated gate detector field effect transistor;
• ii. means connecting the gate of said detector field effect transistor to a storage node of said stage for detection of the level of charge stored at said stage to produce a corresponding detected signal;
• iii. an insulated gate field effect transistor load impedance connected in series with said detector transistor, said load impedance transistor having a selectively variable impedance defining a predetermined weighting factor for weighting the amplitude of said detected signal;
• d. switching means connected to each said detector means for selectively connecting said weighted outputs either to said negative summation bus or to said positive summation bus responsive to a logic signal applied to said switching means;
• e. control means connected to said switching means for simultaneously applying said logic signals to said switching means in a code corresponding to a selectable matched filter function;
• f. output means connected to said summation buses for algebraically summing said weighted detected signals selectively connected to said negative and positive summation buses, said output means comprising:
• i. a pair of insulated gate field effect transistor amplifiers having inputs respectively connected to said negative and positive summation buses;
• and
• ii. a linear insulated gate field effect transistor differential amplifier having a pair of inputs, means connecting said inputs respectively to the outputs of said amplifiers, said differential amplifier providing an output signal for said matched filter which corresponds effectively to the difference between the sum of said weighted detected signals applied to said positive summation bus and the sum of said weighted detected signals applied to said negative summation bus.