Dual density 800 bpi NRZI and 1600 bpi PE read circuit for a digital magnetic tape transport

A read circuit for selectively processing phase encoded and NRZI information generated by a read head of a digital magnetic tape transport, the read circuit comprising:

• a differentiating circuit connected to receive and differentiate a read head signal;
• a squaring circuit connected to receive and square the differentiated read head signal;
• a first EXCLUSIVE-OR gate having one input coupled to receive the squared differentiated signal, a second input coupled to receive a reverse signal which indicates that reading is occurring in a phase encoded format while tape is moving backwards, and an output;
• a first inverter having an input coupled to the output of the first EXCLUSIVE-OR gate and an output;
• a second EXCLUSIVE-OR gate having a first input coupled to the first inverter, a second input connected to a Q output of a toggling flip-flop and an output;
• an intergrating circuit coupled to integrate a signal output by the second EXCLUSIVE-OR gate and generate an integrated differentiated read head signal as an output;
• a latching flip-flop connected to latch a logic 1 data signal when clocked by a high to low transition of a signal output by the second EXCLUSIVE-OR gate while the integrated differentiated read head signal exceeds a selected threshold, the latching flip-flop being further coupled to be reset by a reset signal;
• a first gating circuit coupled to pass an output from the latching flip-flop only when enabled by an NRZI signal indicating that information is being read from magnetic tape in an NRZI format;
• a level detector circuit connected to generate an output signal when a read head signal exceeds a first threshold magnitude with a first polarity while enabled by a Q output of a toggling flip-flop and to generate an output signal when a read head signal exceeds a second threshold magnitude with a second polarity while enabled by a Q output of a toggling flip-flop;
• a toggling flip-flop connected to successively toggle in the absence of an output signal from the level detector circuit, the toggling flip-flop having a Q output coupled to enable first polarity level detection by the comparator circuit and also coupled to the second input of the second EXCLUSIVE-OR gate and a Q output coupled to enable second polarity level detection by the level detection circuit;
• the toggling flip-flop having both its Q and Q outputs active in response to a phase encode signal which indicates the reading of information from magnetic tape in a phase encoded format;
• an envelope detector coupled to indicate by an output signal the appearance of signals at the output of the level detector which are consistent with the reading of phase encoded data from magnetic tape;
• and a second gating circuit coupled to pass signals appearing at the output of the second EXCLUSIVE-OR gate only when enabled by an output signal from the envelope detector and by the phase encode signal.

A read circuit for use in a digital magnetic tape transport having a read head which detects flux transitions on magnetic tape, the read circuit comprising:

• a differentiator responsive to a read head signal which generates a differentiated read head signal as an output;
• a gating circuit having first and second inputs and an output generating a binary output signal which changes with each change of one of the first and second inputs relative to the other, the first input being a Schmitt trigger input which changes from low to high at a first, relatively high threshold, and changes from high to low at a second, relatively low threshold;
• a filter having an input coupled to receive the differentiated read head signal and an output coupled to drive the first input of the gating circuit, the filter circuit permitting successive changes in the first input only with a predetermined minimum time therebetween,
• means for changing the second input at a sufficiently high rate that at least two changes in the second input occur for each change in the first input;
• means for inhibiting changes in the second input during the occurrence of a data pulse on the read head signal;
• an integrator circuit coupled to receive and intergrate the binary output signal from the gating circuit, the integrator circuit generating an integrated, differentiated read head signal as an output;
• a latch coupled to be set at the occurrence of a transition of the binary output signal from the gating circuit when the magnitude of the integrated differentiated read head signal is greater than a predetermined threshold magnitude.