Logical circuit apparatus

Abstract

A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse .phi.1 and a reading-out clock pulse .phi.2 supplied in common thereto and receiving output signals from a Read Only Memory constructed in the form of a matrix. This Read Only Memory is constituted by a plurality of logical gate circuits each supplied with a plurality of prescribed signals of a pulse signal group having a plurality of input signals I1, I2, . . . In and control pulse signals T8, D4, A and B different in frequency from the clock pulses .phi.1 and .phi.2. The logical control circuit includes a first logical gate supplied with a feed back signal from the logical control circuit and a prescribed control pulse signal and a second logical gate supplied with an output signal generated from the corresponding logical gate circuit of the Read Only Memory in accordance with the prescribed control pulse signal and prescribed input signals and with an output signal from the first logical gate the output of the second logical gate is delayed in response to clock pulses .phi.1 and .phi.2 and then is generated as an output signal from the logical control circuit.

Dependencies are inferred from the claim text.