Channel number memory for television tuners
AssigneeRCA Corporation
InventorDon Edward Christensen
Life of this patent
Estimating the term…
Abstract
A voltage controlled tuner in a television receiver is tuned to a desired television channel by sequentially selecting first and second digits representative of a desired channel number. The digits are stored in first and second memory registers from which corresponding analog tuning voltages are developed. Noise immunity circuitry coupled to the memory registers assures accurate registration of the channel digits in the memory registers by minimizing effects of contact bounce and other extraneous noise signals.
Claims10
In a television receiver having means for providing digital signals representative of a channel number, a system for storing said channel number comprising:
- input means for receiving digital signals representative of individual digits of a television channel number;
- means coupled to said input means for detecting the presence of said digital signals;
- delay means coupled to said detecting means for providing a control signal at a predetermined time interval after detection of the presence of said digital signals;
- switching means coupled to said delay means and responsive to successive ones of said control signals for providing alternate first and second output signals;
- and
- first and second register means, each having input terminals coupled to said input means and each having storage enabling terminals coupled to said switching means, said first register being responsive to said first output signal and said second register being responsive to said second output signal for storing, respectively, first and second digit-representative signals supplied by said input means.
In a television receiver having means for providing digital signals representative of a channel number, a system for storing said channel number comprising:
- input means for receiving digital signals representative of individual digits of a television channel number;
- means for detecting the presence of said digital signals;
- integrating means coupled to said means for detecting for providing output signals having amplitude responsive to the duration of said digital signals;
- a first pulse forming means responsive to a predetermined level of said output signal for providing a delayed trigger signal of predetermined width;
- bistable means having first and second output terminals and an input trigger terminal for providing alternate complementary signals at said output terminals in response to said trigger signal;
- second and third pulse forming means respectively coupled to said first and second output terminals of said bistable means for providing pulses of predetermined width in response to signals from said bistable means;
- and
- first and second register means having respective input terminals coupled to said input means and storage enabling terminals respectively coupled to said second and third pulse forming means for respectively storing a first digit representative signal in said first register and a second digit representative signal in said second register in response to signals from said second and third pulse forming means.
Dependencies are inferred from the claim text.