Synchronizing circuit including two flip-flops and circuit means to protect a synchronized signal from an unstable state of the flip-flops

An electronic synchronizing circuit employing two stable flip-flops to synchronize a data signal by a clock signal, said data signal having no fixed phase relation with said clock signal, ensuring the protection of a synchronized signal from an unstable state of said flip-flops comprising:

• a first source of said data signal;
• a second source of said clock signal;
• two flip-flops each having at least an output, a clock input coupled to said second source and a data input;
• at least one delay circuit having an input coupled to said first source and an output coupled to said data input of one of said two flip-flops to couple said data signal to said one of said two flip-flops after a first given time delay greater than a critical period of said two flip-flops;
• said data input of the other of said two flip-flops being coupled to said first source;
• a temporizing circuit having two inputs and an output, one of said two inputs of said temporizing circuit being coupled to said second source to receive said clock signal and the other of said two inputs of said temporizing circuit being coupled to said output of said one of said two flip-flops to receive the output signal of said one of said flip-flops to provide a control signal having a variable delay with respect to said clock signal according to the phase relation between said clock signal and said data signal;
• and
• a logic circuit having at least two inputs and an output, one of said two inputs of said logic circuit being coupled to said output of said temporizing circuit and the other of said two inputs of said logic circuit being coupled to said output of the other of said two flip-flops to provide a stable logical signal at said output of said logic circuit representing the output state of said other of said two flip-flops when said control signal is present.