Digital delay line correlator

Abstract

The correlator disclosed herein detects in a stream of input pulses a plurality of sequences of time spaced signals, each of the plurality of sequences having a different one of a plurality of pulse repetition intervals disposed within a given pulse repetition interval range. This is accomplished by clocking the input pulses into a first shift register by a first clock pulse having a given frequency. N groups of n bistable stages (N being an integer greater than one and n being an integer greater than zero) are disposed at different spaced time positions along the first register corresponding to the pulse repetition intervals and the pulse repetition interval range. First logic circuitry is coupled to each of the N groups of n stages to provide an output pulse when the time spaced pulses of the plurality of sequences of time spaced pulses are simultaneously present at appropriate ones of the n stages of a given number of the N groups of n stages. A second shift register receives on its input stage the output pulse from the first logic circuitry. The output pulse is clocked through the second register by a second clock pulse having the given frequency but phase shifted relative to the first clock pulse. The length of the second register is determined by the plurality of pulse repetition intervals. A plurality of stages at the end of the second register produce through second logic circuitry a gate pulse which predicts when the next pulse of each of the plurality of sequences should occur. Several embodiments are disclosed which enable the production of the output signal from the first logic circuitry when all the pulses of the plurality of sequences are present or when there is a pulse missing from any of the plurality of sequences. An additional embodiment is disclosed which enables the detection of M plurality of sequences of time spaced pulses when only (N-1) out of N pulses of each of the M plurality of sequences are present employing M first logic circuitry. A gate signal is produced by the second register and second logic circuitry for each of the output signals from the M first logic circuitry to predict when the next pulse of each of the plurality of sequences of the M plurality of sequence should occur.

Dependencies are inferred from the claim text.