Binary parallel computing arrangement for additions or subtractions

A parallel binary computing arrangement comprising:

• an adder having a plurality of stages with sequential carry propagation between stages, each stage receiving corresponding digit positions of two operands,
• a plurality of detection circuits distributed over the stages of said adder, each said detection circuit receiving the operand digits of at least one digit position of each operand for providing a detector output signal indicating the beginning or the end of a carry ripple by testing the condition "both operand digits 0 or both operand digits 1",
• a coder connected and responsive to the output signals of said detection circuits for providing one of a plurality of group indicating signals, each of which corresponds to a predetermined distance of possible carry ripples between digit positions,
• a clock including pulse generating means for providing a repeatable sequence of a predetermined number of time pulses;
• and
• clock modifying means, responsive to said group indicating signals from said coder for selectively skipping certain of said time pulses, whereby the operating time between the starting time of said clock sequence if limited to the duration of the carry ripple over the shortest digit position distance determined by said detection circuits.