Signed multiplication logic

Signed multiplication logic for multiplying two serial binary numbers to obtain a serial binary product, the multiplicand containing magnitude and sign information in two's complement notation, the multiplier containing magnitude information and the product containing magnitude and sign information in two's complement notation, said multiplier, multiplicand and product bit streams occurring serially at equal word rates with the least significant bit first in time, said multiplication logic comprising:

• a. a bus to which the multiplier bit stream is supplied in words of an "n" plurality of bits,
• b. an "n" plurality of binary storage elements coupled to said bus for storing the successive words of said multiplier bit stream, each storage element selecting a bit a pre-determined significance from each word of said multiplier bit stream and storing said selected bit until a bit of like significance occurs in the succeeding word,
• c. a shift register having an "n" plurality of connections at one bit intervals to which the multiplicand bit stream is supplied,
• d. an "n" plurality of multiplication stages, each connected for multiplier bit entry to a binary storage element and for multiplicand entry to a connection of said multiplicand shift register whose accummulated bits of delay increase in correspondence with the significance of the multiplier bit entered, each stage multiplying a consecutive selection of the most significant bits of a word of the multiplicand by a multiplier bit to form a serial partial product timed in correspondence with its significance, and
• e. a summation network coupled to the output of each of said multiplication stages for consolidating the bit streams representing said partial products into a single bit stream equal to the product.