Multi-emitter transistor having heavily doped N+ regions surrounding base region of transistors

In a multi-emitter transistor structure, said multi-emitter transistor structure being doped with a lifetime killer material, comprising:

• a collector region of a first conductivity type;
• a base region of a second conductivity type formed in said collector region;
• a plurality of emitter regions of the first conductivity type formed in said base region;
• and
• a heavily doped contact region of the first conductivity type formed in said collector region for collector ohmic contact, said heavily doped contact region being formed along only part of the periphery of the base region for decreasing the current amplification in the lateral direction;
• the improvement comprising that said structure further comprises a further region of said second conductivity type surrounding said base region at a common surface of said collector region and said further region;
• and
• an N-type heavily doped region formed in said further region, so as to substantially surround said base region, wherein said first conductivity type is N-type, and said second conductivity type is P-type.

In a multi-emitter transistor structure said multi-emitter structure being doped with a life time killer material, comprising:

• an N-type collector region;
• a P-type base region formed in said collector region;
• a plurality of N-type emitter regions formed in said base region;
• and
• a heavily doped N-type contact region formed in said collector region for the collector ohmic contact, said heavily doped contact region being formed along only part of the periphery of the base region for decreasing the current amplification in the lateral direction;
• the improvement comprising that said structure further comprises a P-type further region along said base region at a common surface of said collector region and said further region;
• and
• an N-type heavily doped region formed in said further region, so as to substantially surround said base region by itself or in cooperation with said heavily doped contact region.

An integrated circuit device comprising a semiconductor substrate of a first conductivity type having a major surface;

• a plurality of semiconductor regions of a second conductivity type disposed on said major surface of the substrate so as to be spaced from each other and so as to have a common surface, at least one of the semiconductor regions including a base region of the first conductivity type and an emitter region of the second conductivity type formed in said base region so as to constitute a transistor, at least one of the semiconductor regions being doped with a life time killer material;
• an isolation region of the first conductivity type semiconductor material disposed on the major surface of the substrate among said plurality of semiconductor regions and defining PN junctions terminating at said common surface with said plurality of semiconductor regions, respectively;
• and auxiliary means including at least one heavily doped N-type region formed in said isolation region so as to surround the base region of said transistor at said common surface, wherein said first conductivity type is a P-type, and said second conductivity type is an N-type, and wherein at least some of the semiconductor regions include P-type base regions and N-type emitter regions formed in said base regions, respectively, so as to constitute a plurality of NPN-type transistors, said auxiliary means includes a plurality of heavily doped N-type regions formed in said isolation region and in at least one of said semiconductor regions so as to surround all of the base regions of said transistors at said common surface, respectively.