System for compensating voltage for a CCD sensing circuit
AssigneeIntel Corporation
InventorSunlin Chou
Life of this patent
Estimating the term…
Abstract
A system for providing a compensated voltage used for precharging the detector/refreshing amplifiers in a charge-coupled memory employing a plurality of shift registers. A pair of dummy registers are used to generate a reference register output signal which is applied to a dummy sensor. The output of the dummy sensor is used to control, through a current source, the compensated voltage; the compensated voltage is used to pre-charge the dummy sensor. The system is particularly adaptable for an MOS CCD memory employing two layer polycrystalline silicon technology.
Claims15
An apparatus for providing a regulated potential in an MOS-CCD memory which includes a plurality of charge-coupled memory shift registers for storing information comprising:
- a pulse supply means including a charge-coupled shift register for generating a register reference output signal;
- a sensor having an output and an input coupled to said register output signal for sensing said register reference output signal;
- a regulating means for providing a regulated output potential, said regulating means being controlled by said output of said sensor;
- and
- feedback means, for feeding back at least a portion of said regulated output potential to said sensor;
- whereby said regulatd output potential may be used in the sensing of information stored in said memory shift registers.
In a CCD memory system disposed on a substrate employing at least one sensing transistor for sensing the output of a storage shift register, an improvement for generating a reference potential for said sensing transistor comprising:
- a shift register having the same general geometry as said storage shift register, disposed on said substrate;
- and
- voltage generation means for generating said reference potential, said generation means being controlled, at least in part, by said shift register;
- whereby said improvement compensates for parameter variations on said substrate.
In a circuit for sensing the output charge from a charge-coupled storage shift register which includes a sensing node for receiving said output charge, an improvement for adjusting said output charge on said sensing node as a function of non-programmed variations in the magnitude of said charge where said circuit and said shift register are disposed on a common substrate comprising:
- a reference shift register disposed on said common substrate;
- signal generation means for generating an input signal for said reference shift register coupled to said reference shift register;
- voltage generation means for generating an adjustment signal;
- and
- comparator means for comparing the output of said reference shift register with said adjustment signal and for controlling said voltage generation means, coupled to said reference shift register and said voltage generation means;
- whereby said adjustment signal may be used to adjust said output charge on said sensing node thereby providing improved sensing of charge from said storage shift register.
In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors for sensing the output of said storage shift registers, a system for generating a reference potential which is coupled to said sensing transistors comprising:
- at least one generation means for generating a signal representative of a binary state;
- at least one reference register coupled to said generation means, said reference register having at least one channel of approximately the same length and width as a channel of said storage shift register;
- a reference sensing transistor having the same general characteristics as said sensing transistors, said reference sensing transistor having its gate coupled to the output of said reference register and also having its gate selectively coupled to said reference potential, said reference sensing transistor having an output control signal line;
- an output transistor for controlling said reference potential, said output transistor having a gate;
- a first current source coupled to said gate of said output transistor;
- a variable current source coupled to said gate of said output transistor, said variable current source being coupled to said output control signal line of said reference sensing transistor;
- whereby said reference potential will vary as a function of the output of said reference register and as a function of variations in said reference sensing transistor.
In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors, a system for generating a reference potential coupled to said sensing transistors comprising;
- a register having a first and a second channel, each of said channels being of approximately the same length and width as a channel of said storage registers;
- a first generation means for generating a charge representing a first binary state, coupled to said first channel;
- a second generation means for generating a charge representing a second binary state coupled to said second channel;
- a cross channel interconnecting said first and second channels;
- a transistor for providing a control signal having its gate coupled to the output of said register, said gate being selectively coupled to said reference potential;
- an output transistor for controlling said reference potential, said output transistor including a gate;
- a first current source including a channel coupled to said gate of said output transistor;
- and
- a second current source including a channel coupled to said gate of said output transistor, said second current source being controlled by said control signal of said transistor;
- whereby the output of said output transistor may be used by said sensing transistor in sensing of charge from said storage shift registers.
Dependencies are inferred from the claim text.